Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4560052	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

20389848

1

T22

203

T23

982

T1

3522

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	9951908	1			T22	130		T23	1188		T1	2344
values[0x0]	7370552	1			T22	63		T23	204		T1	1211
values[0x1]	7627440	1			T22	81		T23	183		T1	1145

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3505849	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

21444051

1

T22

218

T23

1094

T1

3776

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	98678	1			T1	18		T13	5		T15	2
valid_sources[0x01]	85990	1			T1	12		T15	1		T17	1
valid_sources[0x02]	167492	1			T1	20		T13	2		T16	1
valid_sources[0x03]	91532	1			T1	21		T13	5		T15	2
valid_sources[0x04]	88995	1			T1	12		T12	1		T13	1
valid_sources[0x05]	88017	1			T1	16		T13	3		T15	3
valid_sources[0x06]	90550	1			T22	1		T1	12		T13	8
valid_sources[0x07]	88920	1			T1	26		T15	1		T18	17
valid_sources[0x08]	85946	1			T22	9		T1	16		T13	3
valid_sources[0x09]	87662	1			T22	1		T1	28		T15	2
valid_sources[0x0a]	87205	1			T1	13		T15	2		T16	2
valid_sources[0x0b]	86668	1			T22	1		T1	16		T13	1
valid_sources[0x0c]	91359	1			T1	18		T13	2		T16	1
valid_sources[0x0d]	89848	1			T22	3		T23	1575		T1	16
valid_sources[0x0e]	94699	1			T1	13		T15	2		T18	11
valid_sources[0x0f]	95800	1			T1	18		T13	5		T15	3
valid_sources[0x10]	95692	1			T1	29		T15	2		T18	20
valid_sources[0x11]	85897	1			T1	15		T15	3		T17	4
valid_sources[0x12]	86105	1			T1	16		T12	1		T13	1
valid_sources[0x13]	88497	1			T1	15		T17	6		T18	6
valid_sources[0x14]	91525	1			T1	13		T13	1		T15	1
valid_sources[0x15]	167291	1			T1	13		T11	79977		T13	3
valid_sources[0x16]	98102	1			T1	25		T15	1		T17	7
valid_sources[0x17]	97754	1			T1	15		T15	2		T17	1
valid_sources[0x18]	88605	1			T22	1		T1	15		T13	4
valid_sources[0x19]	86671	1			T1	22		T12	3		T13	1
valid_sources[0x1a]	84530	1			T22	1		T1	17		T13	2
valid_sources[0x1b]	97133	1			T22	1		T1	10		T13	4
valid_sources[0x1c]	93131	1			T1	8		T15	3		T16	2
valid_sources[0x1d]	82727	1			T1	14		T15	1		T18	10
valid_sources[0x1e]	94457	1			T1	21		T13	1		T15	2
valid_sources[0x1f]	86186	1			T22	3		T1	13		T12	1
valid_sources[0x20]	88769	1			T1	24		T15	2		T16	1
valid_sources[0x21]	85791	1			T1	17		T15	3		T2	161
valid_sources[0x22]	141971	1			T1	21		T13	2		T15	1
valid_sources[0x23]	88361	1			T22	1		T1	19		T15	3
valid_sources[0x24]	93969	1			T1	14		T12	6		T15	2
valid_sources[0x25]	88104	1			T22	5		T1	20		T15	1
valid_sources[0x26]	87362	1			T22	2		T1	22		T12	1
valid_sources[0x27]	98235	1			T1	26		T15	2		T18	8
valid_sources[0x28]	91871	1			T1	11		T16	1		T18	13
valid_sources[0x29]	91186	1			T1	25		T15	1		T16	1
valid_sources[0x2a]	86852	1			T1	13		T12	1		T13	2
valid_sources[0x2b]	90851	1			T1	24		T17	1		T18	5
valid_sources[0x2c]	86701	1			T22	2		T1	18		T13	1
valid_sources[0x2d]	79144	1			T22	3		T1	24		T13	2
valid_sources[0x2e]	92809	1			T22	3		T1	17		T13	1
valid_sources[0x2f]	86435	1			T1	11		T13	5		T15	1
valid_sources[0x30]	90485	1			T22	3		T1	14		T13	1
valid_sources[0x31]	278680	1			T1	17		T15	4		T18	3
valid_sources[0x32]	90990	1			T1	14		T13	1		T15	3
valid_sources[0x33]	96144	1			T1	19		T13	3		T15	3
valid_sources[0x34]	96853	1			T1	19		T15	2		T16	1
valid_sources[0x35]	90423	1			T1	23		T15	3		T18	21
valid_sources[0x36]	87565	1			T1	15		T15	1		T16	1
valid_sources[0x37]	87159	1			T22	2		T1	19		T12	1
valid_sources[0x38]	288112	1			T1	24		T12	3		T13	1
valid_sources[0x39]	242557	1			T22	1		T1	21		T15	5
valid_sources[0x3a]	88440	1			T1	22		T13	1		T15	2
valid_sources[0x3b]	91530	1			T1	17		T18	12		T115	19
valid_sources[0x3c]	90245	1			T22	3		T1	14		T15	2
valid_sources[0x3d]	96743	1			T1	32		T13	7		T15	1
valid_sources[0x3e]	91338	1			T1	14		T13	4		T15	4
valid_sources[0x3f]	89751	1			T1	21		T16	1		T18	16
valid_sources[0x40]	87331	1			T22	2		T1	22		T15	3
valid_sources[0x41]	87397	1			T22	2		T1	13		T15	5
valid_sources[0x42]	92266	1			T1	18		T13	1		T15	2
valid_sources[0x43]	90662	1			T1	15		T15	1		T18	10
valid_sources[0x44]	84612	1			T1	7		T16	2		T17	15
valid_sources[0x45]	89115	1			T1	17		T15	1		T18	11
valid_sources[0x46]	92379	1			T1	16		T15	1		T16	2
valid_sources[0x47]	85742	1			T22	3		T1	17		T12	1
valid_sources[0x48]	89316	1			T22	2		T1	23		T13	4
valid_sources[0x49]	86635	1			T22	1		T1	17		T13	2
valid_sources[0x4a]	95583	1			T1	23		T12	2		T13	1
valid_sources[0x4b]	89205	1			T1	18		T15	1		T18	14
valid_sources[0x4c]	97648	1			T22	4		T1	22		T15	4
valid_sources[0x4d]	89641	1			T22	2		T1	14		T13	1
valid_sources[0x4e]	92393	1			T1	22		T13	1		T16	1
valid_sources[0x4f]	84109	1			T1	26		T13	1		T16	1
valid_sources[0x50]	88746	1			T1	16		T13	3		T15	1
valid_sources[0x51]	92162	1			T22	1		T1	22		T13	4
valid_sources[0x52]	83396	1			T1	22		T13	1		T15	4
valid_sources[0x53]	92924	1			T22	3		T1	30		T13	1
valid_sources[0x54]	97226	1			T1	25		T16	1		T18	16
valid_sources[0x55]	83412	1			T1	15		T13	3		T15	2
valid_sources[0x56]	96462	1			T1	17		T13	1		T15	3
valid_sources[0x57]	84602	1			T22	2		T1	20		T13	1
valid_sources[0x58]	88402	1			T1	19		T15	1		T17	2
valid_sources[0x59]	81311	1			T1	24		T15	3		T17	2
valid_sources[0x5a]	100175	1			T1	15		T13	4		T15	1
valid_sources[0x5b]	90404	1			T1	15		T15	3		T18	10
valid_sources[0x5c]	81963	1			T22	15		T1	27		T13	2
valid_sources[0x5d]	87401	1			T22	2		T1	27		T13	1
valid_sources[0x5e]	90901	1			T1	21		T13	2		T15	3
valid_sources[0x5f]	85110	1			T1	28		T15	1		T16	1
valid_sources[0x60]	94165	1			T1	27		T15	3		T17	1
valid_sources[0x61]	93415	1			T1	18		T15	1		T18	23
valid_sources[0x62]	88483	1			T22	1		T1	34		T13	3
valid_sources[0x63]	93525	1			T22	2		T1	23		T13	1
valid_sources[0x64]	90096	1			T22	8		T1	22		T12	3
valid_sources[0x65]	88635	1			T1	24		T15	1		T18	19
valid_sources[0x66]	87563	1			T1	23		T18	18		T116	10
valid_sources[0x67]	92394	1			T1	11		T13	1		T15	2
valid_sources[0x68]	94542	1			T1	17		T15	1		T17	2
valid_sources[0x69]	90641	1			T22	1		T1	19		T15	2
valid_sources[0x6a]	90802	1			T1	15		T15	1		T18	6
valid_sources[0x6b]	87235	1			T22	12		T1	20		T12	4
valid_sources[0x6c]	93564	1			T1	23		T15	3		T17	6
valid_sources[0x6d]	93829	1			T22	11		T1	17		T15	1
valid_sources[0x6e]	86964	1			T22	2		T1	12		T15	1
valid_sources[0x6f]	92391	1			T1	20		T15	2		T16	1
valid_sources[0x70]	94088	1			T1	16		T13	1		T15	2
valid_sources[0x71]	82990	1			T22	1		T1	21		T15	1
valid_sources[0x72]	90202	1			T1	19		T12	1		T15	3
valid_sources[0x73]	86880	1			T22	2		T1	12		T16	1
valid_sources[0x74]	88099	1			T22	3		T1	15		T18	6
valid_sources[0x75]	93222	1			T1	25		T13	2		T15	2
valid_sources[0x76]	85035	1			T22	3		T1	8		T13	1
valid_sources[0x77]	91440	1			T1	21		T13	1		T16	3
valid_sources[0x78]	91562	1			T1	21		T13	4		T15	3
valid_sources[0x79]	95821	1			T1	9		T12	1		T13	2
valid_sources[0x7a]	85002	1			T22	6		T1	26		T15	3
valid_sources[0x7b]	92106	1			T22	1		T1	18		T15	2
valid_sources[0x7c]	90743	1			T1	30		T13	4		T15	3
valid_sources[0x7d]	91313	1			T1	19		T15	3		T16	1
valid_sources[0x7e]	96823	1			T1	16		T17	2		T18	18
valid_sources[0x7f]	93186	1			T1	22		T12	4		T15	1
valid_sources[0x80]	94408	1			T1	19		T13	5		T15	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5697060

1

T22

59

T23

595

T1

1166

values[0x0]

all_enables

biggest_size

7344775

1

T22

63

T23

204

T1

1211

values[0x1]

all_enables

biggest_size

7348013

1

T22

81

T23

183

T1

1145