Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4516655	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

20016699

1

T32

17468

T1

110

T11

223

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	9836300	1			T32	9636		T1	16		T11	27
values[0x0]	7226693	1			T32	6436		T1	51		T11	99
values[0x1]	7470361	1			T32	6191		T1	52		T11	109

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3476218	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

21057136

1

T32

18449

T1

113

T11

226

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	87043	1			T32	86		T13	2829		T14	1
valid_sources[0x01]	88907	1			T32	39		T12	1		T13	2822
valid_sources[0x02]	102222	1			T32	96		T13	2859		T14	1
valid_sources[0x03]	82362	1			T32	95		T1	7		T12	2
valid_sources[0x04]	93020	1			T32	68		T13	2962		T14	2
valid_sources[0x05]	90001	1			T32	118		T12	1		T13	2819
valid_sources[0x06]	258696	1			T32	103		T13	3073		T14	1
valid_sources[0x07]	95635	1			T32	63		T13	2912		T14	3
valid_sources[0x08]	88395	1			T32	87		T13	2957		T16	1
valid_sources[0x09]	108458	1			T32	112		T12	1		T13	2925
valid_sources[0x0a]	231016	1			T32	51		T13	2856		T17	36
valid_sources[0x0b]	98128	1			T32	75		T12	3		T13	2965
valid_sources[0x0c]	92969	1			T32	47		T13	2889		T14	1
valid_sources[0x0d]	95674	1			T32	68		T12	4		T13	3037
valid_sources[0x0e]	91292	1			T32	76		T12	2		T13	2996
valid_sources[0x0f]	89533	1			T32	103		T13	3079		T17	22
valid_sources[0x10]	97023	1			T32	126		T12	2		T13	2815
valid_sources[0x11]	93887	1			T32	84		T13	2884		T14	3
valid_sources[0x12]	93692	1			T32	102		T12	1		T13	3046
valid_sources[0x13]	86320	1			T32	76		T13	2937		T14	1
valid_sources[0x14]	93008	1			T32	29		T12	1		T13	2861
valid_sources[0x15]	83621	1			T32	84		T12	4		T13	2848
valid_sources[0x16]	101228	1			T32	98		T12	2		T13	2905
valid_sources[0x17]	93836	1			T32	57		T12	4		T13	2929
valid_sources[0x18]	97888	1			T32	78		T13	2893		T14	1
valid_sources[0x19]	120567	1			T32	62		T13	2873		T14	3
valid_sources[0x1a]	242690	1			T32	134		T13	2837		T17	24
valid_sources[0x1b]	92478	1			T32	72		T13	2950		T14	4
valid_sources[0x1c]	97704	1			T32	72		T12	2		T13	2968
valid_sources[0x1d]	86927	1			T32	28		T13	2909		T14	2
valid_sources[0x1e]	86434	1			T32	126		T12	3		T13	2886
valid_sources[0x1f]	95608	1			T32	97		T13	3012		T14	1
valid_sources[0x20]	82086	1			T32	91		T12	2		T13	2748
valid_sources[0x21]	87186	1			T32	76		T12	1		T13	2999
valid_sources[0x22]	87758	1			T32	83		T12	2		T13	3008
valid_sources[0x23]	100527	1			T32	112		T12	1		T13	2832
valid_sources[0x24]	91908	1			T32	77		T13	3025		T14	1
valid_sources[0x25]	85596	1			T32	79		T12	2		T13	2836
valid_sources[0x26]	82353	1			T32	54		T12	8		T13	2816
valid_sources[0x27]	87001	1			T32	50		T13	2900		T14	1
valid_sources[0x28]	98661	1			T32	85		T13	2870		T14	5
valid_sources[0x29]	102610	1			T32	92		T13	2903		T14	3
valid_sources[0x2a]	95304	1			T32	48		T13	2948		T14	2
valid_sources[0x2b]	86495	1			T32	104		T12	2		T13	3013
valid_sources[0x2c]	101887	1			T32	73		T12	2		T13	2975
valid_sources[0x2d]	90552	1			T32	167		T12	3		T13	3017
valid_sources[0x2e]	92480	1			T32	120		T12	1		T13	2933
valid_sources[0x2f]	91910	1			T32	131		T13	2887		T17	15
valid_sources[0x30]	87798	1			T32	78		T13	2898		T14	4
valid_sources[0x31]	91374	1			T32	80		T13	2911		T14	2
valid_sources[0x32]	85262	1			T32	62		T13	2952		T14	3
valid_sources[0x33]	80654	1			T32	130		T13	2893		T14	2
valid_sources[0x34]	95305	1			T32	84		T12	1		T13	2977
valid_sources[0x35]	88550	1			T32	66		T11	235		T13	2992
valid_sources[0x36]	94940	1			T32	117		T12	2		T13	2891
valid_sources[0x37]	85021	1			T32	118		T13	2988		T14	4
valid_sources[0x38]	95628	1			T32	127		T12	1		T13	2906
valid_sources[0x39]	81994	1			T32	79		T13	2913		T14	3
valid_sources[0x3a]	81368	1			T32	103		T13	2888		T14	3
valid_sources[0x3b]	86358	1			T32	77		T13	2910		T14	2
valid_sources[0x3c]	84179	1			T32	116		T12	3		T13	2892
valid_sources[0x3d]	74806	1			T32	46		T12	1		T13	2966
valid_sources[0x3e]	98934	1			T32	89		T12	1		T13	3008
valid_sources[0x3f]	86938	1			T32	70		T13	2855		T17	10
valid_sources[0x40]	83151	1			T32	74		T13	2877		T14	4
valid_sources[0x41]	90037	1			T32	83		T13	2844		T14	1
valid_sources[0x42]	242960	1			T32	50		T13	2922		T14	5
valid_sources[0x43]	89308	1			T32	160		T13	2794		T14	3
valid_sources[0x44]	93806	1			T32	54		T13	2886		T14	2
valid_sources[0x45]	77705	1			T32	86		T12	2		T13	2909
valid_sources[0x46]	88808	1			T32	52		T13	2774		T14	2
valid_sources[0x47]	89250	1			T32	64		T13	2870		T14	1
valid_sources[0x48]	86283	1			T32	55		T13	2976		T14	1
valid_sources[0x49]	92669	1			T32	96		T12	1		T13	2830
valid_sources[0x4a]	94475	1			T32	113		T12	1		T13	2973
valid_sources[0x4b]	90273	1			T32	137		T12	1		T13	2897
valid_sources[0x4c]	104007	1			T32	48		T13	2938		T14	2
valid_sources[0x4d]	94639	1			T32	76		T13	2968		T14	2
valid_sources[0x4e]	87494	1			T32	83		T13	2992		T14	1
valid_sources[0x4f]	81178	1			T32	107		T13	2897		T14	4
valid_sources[0x50]	86812	1			T32	118		T1	11		T13	2907
valid_sources[0x51]	90034	1			T32	80		T12	3		T13	3032
valid_sources[0x52]	95714	1			T32	62		T12	7		T13	2923
valid_sources[0x53]	77976	1			T32	49		T12	1		T13	2965
valid_sources[0x54]	92037	1			T32	53		T12	1		T13	2836
valid_sources[0x55]	94229	1			T32	124		T1	3		T12	2
valid_sources[0x56]	92805	1			T32	121		T13	2941		T14	3
valid_sources[0x57]	81153	1			T32	55		T13	2947		T14	2
valid_sources[0x58]	93305	1			T32	99		T12	2		T13	3077
valid_sources[0x59]	85005	1			T32	73		T1	6		T12	1
valid_sources[0x5a]	97915	1			T32	65		T12	1		T13	2905
valid_sources[0x5b]	82499	1			T32	113		T12	1		T13	2965
valid_sources[0x5c]	104109	1			T32	131		T12	2		T13	2897
valid_sources[0x5d]	92441	1			T32	91		T12	3		T13	2866
valid_sources[0x5e]	86105	1			T32	93		T13	2955		T14	1
valid_sources[0x5f]	99969	1			T32	58		T13	3056		T14	2
valid_sources[0x60]	95491	1			T32	67		T13	2861		T14	2
valid_sources[0x61]	82800	1			T32	60		T12	3		T13	2991
valid_sources[0x62]	84909	1			T32	96		T13	2939		T14	3
valid_sources[0x63]	86416	1			T32	93		T12	1		T13	2819
valid_sources[0x64]	102905	1			T32	136		T12	1		T13	2827
valid_sources[0x65]	96499	1			T32	112		T13	2848		T14	1
valid_sources[0x66]	91217	1			T32	94		T12	2		T13	2944
valid_sources[0x67]	90627	1			T32	79		T13	2861		T14	4
valid_sources[0x68]	85766	1			T32	116		T13	2794		T14	5
valid_sources[0x69]	86806	1			T32	82		T13	2995		T14	2
valid_sources[0x6a]	83723	1			T32	94		T12	2		T13	2898
valid_sources[0x6b]	94293	1			T32	72		T12	1		T13	2957
valid_sources[0x6c]	96796	1			T32	77		T13	2912		T14	5
valid_sources[0x6d]	110598	1			T32	105		T1	2		T13	2931
valid_sources[0x6e]	84960	1			T32	113		T13	2839		T14	2
valid_sources[0x6f]	90711	1			T32	68		T13	2931		T14	2
valid_sources[0x70]	96639	1			T32	69		T13	2947		T14	2
valid_sources[0x71]	92084	1			T32	117		T13	2904		T17	57
valid_sources[0x72]	93265	1			T32	93		T13	2897		T14	2
valid_sources[0x73]	88529	1			T32	97		T12	4		T13	2750
valid_sources[0x74]	86967	1			T32	72		T13	2853		T14	1
valid_sources[0x75]	88724	1			T32	64		T12	5		T13	2948
valid_sources[0x76]	87548	1			T32	85		T12	4		T13	2921
valid_sources[0x77]	88901	1			T32	122		T13	3002		T17	12
valid_sources[0x78]	95679	1			T32	87		T12	2		T13	2892
valid_sources[0x79]	89711	1			T32	90		T1	2		T12	1
valid_sources[0x7a]	93439	1			T32	158		T12	1		T13	2997
valid_sources[0x7b]	107374	1			T32	74		T13	2892		T17	2
valid_sources[0x7c]	97887	1			T32	126		T12	2		T13	2918
valid_sources[0x7d]	86763	1			T32	80		T12	2		T13	2907
valid_sources[0x7e]	89333	1			T32	121		T1	1		T12	1
valid_sources[0x7f]	91498	1			T32	97		T13	3024		T14	3
valid_sources[0x80]	83721	1			T32	71		T13	2982		T17	16

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5611854

1

T32

4841

T1

7

T11

15

values[0x0]

all_enables

biggest_size

7202499

1

T32

6436

T1

51

T11

99

values[0x1]

all_enables

biggest_size

7202346

1

T32

6191

T1

52

T11

109