Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	183702108	0	0	0
ctrl_en_input_filter_rd_A	183702108	84260	0	0
intr_ctrl_en_falling_rd_A	183702108	86434	0	0
intr_ctrl_en_lvlhigh_rd_A	183702108	84915	0	0
intr_ctrl_en_lvllow_rd_A	183702108	86469	0	0
intr_ctrl_en_rising_rd_A	183702108	84383	0	0
intr_enable_rd_A	183702108	84888	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183702108	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183702108	84260	0	0
T1	4724	3	0	0
T2	0	2854	0	0
T3	0	2	0	0
T4	0	6521	0	0
T5	0	1058	0	0
T6	0	146	0	0
T7	0	382	0	0
T8	0	643	0	0
T9	0	6127	0	0
T10	0	2	0	0
T11	6079	0	0	0
T12	3595	0	0	0
T13	563571	0	0	0
T14	9690	0	0	0
T15	1019	0	0	0
T16	4314	0	0	0
T17	53104	0	0	0
T18	3100	0	0	0
T19	3997	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183702108	86434	0	0
T2	774107	2851	0	0
T3	0	3	0	0
T4	0	6371	0	0
T5	0	1131	0	0
T6	0	202	0	0
T7	0	303	0	0
T8	0	647	0	0
T9	0	6516	0	0
T20	0	2	0	0
T21	0	8	0	0
T22	4411	0	0	0
T23	8513	0	0	0
T24	5576	0	0	0
T25	5615	0	0	0
T26	6930	0	0	0
T27	1250	0	0	0
T28	7407	0	0	0
T29	5063	0	0	0
T30	28486	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183702108	84915	0	0
T2	774107	2774	0	0
T3	0	9	0	0
T4	0	6512	0	0
T5	0	1095	0	0
T6	0	149	0	0
T7	0	207	0	0
T8	0	636	0	0
T9	0	6094	0	0
T20	0	2	0	0
T22	4411	0	0	0
T23	8513	0	0	0
T24	5576	0	0	0
T25	5615	0	0	0
T26	6930	0	0	0
T27	1250	0	0	0
T28	7407	0	0	0
T29	5063	0	0	0
T30	28486	0	0	0
T31	0	250	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183702108	86469	0	0
T1	4724	8	0	0
T2	0	2638	0	0
T3	0	1	0	0
T4	0	6443	0	0
T5	0	1109	0	0
T6	0	148	0	0
T7	0	228	0	0
T8	0	607	0	0
T9	0	5773	0	0
T11	6079	0	0	0
T12	3595	0	0	0
T13	563571	0	0	0
T14	9690	0	0	0
T15	1019	0	0	0
T16	4314	0	0	0
T17	53104	0	0	0
T18	3100	0	0	0
T19	3997	0	0	0
T31	0	249	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183702108	84383	0	0
T1	4724	3	0	0
T2	0	2703	0	0
T3	0	9	0	0
T4	0	6195	0	0
T5	0	1034	0	0
T6	0	140	0	0
T7	0	326	0	0
T8	0	731	0	0
T9	0	5721	0	0
T11	6079	0	0	0
T12	3595	0	0	0
T13	563571	0	0	0
T14	9690	0	0	0
T15	1019	0	0	0
T16	4314	0	0	0
T17	53104	0	0	0
T18	3100	0	0	0
T19	3997	0	0	0
T20	0	8	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183702108	84888	0	0
T2	774107	2818	0	0
T4	0	6200	0	0
T5	0	1164	0	0
T6	0	179	0	0
T7	0	250	0	0
T8	0	643	0	0
T9	0	6241	0	0
T10	0	7	0	0
T20	0	4	0	0
T22	4411	0	0	0
T23	8513	0	0	0
T24	5576	0	0	0
T25	5615	0	0	0
T26	6930	0	0	0
T27	1250	0	0	0
T28	7407	0	0	0
T29	5063	0	0	0
T30	28486	0	0	0
T31	0	286	0	0