Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3155134	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

13360917

1

T18

81

T19

105

T20

1296

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	6758765	1			T18	25		T19	23		T20	1557
values[0x0]	4810329	1			T18	37		T19	52		T20	265
values[0x1]	4946957	1			T18	34		T19	44		T20	246

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2447017	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

14069034

1

T18

86

T19

107

T20

1457

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	66082	1			T20	8		T23	16		T2	322
valid_sources[0x01]	58200	1			T18	1		T20	5		T22	3
valid_sources[0x02]	59247	1			T20	1		T23	15		T2	296
valid_sources[0x03]	64053	1			T20	8		T22	1		T23	13
valid_sources[0x04]	60654	1			T18	1		T20	12		T22	1
valid_sources[0x05]	64200	1			T18	1		T20	11		T22	2
valid_sources[0x06]	52535	1			T20	11		T22	1		T23	13
valid_sources[0x07]	58610	1			T18	1		T20	6		T23	17
valid_sources[0x08]	60898	1			T18	1		T20	11		T22	3
valid_sources[0x09]	65288	1			T19	3		T20	8		T22	4
valid_sources[0x0a]	58405	1			T20	14		T22	2		T23	11
valid_sources[0x0b]	60889	1			T20	3		T22	1		T23	16
valid_sources[0x0c]	58527	1			T20	14		T22	1		T23	18
valid_sources[0x0d]	64429	1			T20	8		T22	1		T23	16
valid_sources[0x0e]	57454	1			T20	9		T22	1		T23	17
valid_sources[0x0f]	62716	1			T20	3		T22	1		T23	14
valid_sources[0x10]	66587	1			T18	1		T20	7		T23	15
valid_sources[0x11]	52967	1			T20	14		T23	9		T2	287
valid_sources[0x12]	59539	1			T20	4		T22	2		T23	20
valid_sources[0x13]	61013	1			T20	5		T23	14		T2	319
valid_sources[0x14]	56155	1			T19	13		T20	8		T23	16
valid_sources[0x15]	54114	1			T18	1		T20	5		T21	2
valid_sources[0x16]	57408	1			T20	13		T22	3		T23	18
valid_sources[0x17]	52176	1			T20	6		T22	1		T23	13
valid_sources[0x18]	60949	1			T20	3		T22	1		T23	10
valid_sources[0x19]	53668	1			T20	19		T23	10		T2	353
valid_sources[0x1a]	60280	1			T18	1		T20	15		T22	2
valid_sources[0x1b]	72721	1			T20	6		T22	1		T23	10
valid_sources[0x1c]	50768	1			T20	2		T23	15		T2	325
valid_sources[0x1d]	52401	1			T20	11		T22	5		T23	18
valid_sources[0x1e]	56135	1			T20	6		T22	1		T23	11
valid_sources[0x1f]	153871	1			T20	2		T22	2		T23	13
valid_sources[0x20]	66515	1			T18	2		T20	4		T22	1
valid_sources[0x21]	61528	1			T20	4		T23	8		T2	316
valid_sources[0x22]	61856	1			T20	9		T22	2		T23	19
valid_sources[0x23]	57766	1			T18	2		T20	8		T23	13
valid_sources[0x24]	56502	1			T20	4		T22	2		T23	8
valid_sources[0x25]	58281	1			T18	1		T20	14		T22	1
valid_sources[0x26]	58053	1			T20	5		T22	2		T23	11
valid_sources[0x27]	65044	1			T20	14		T22	2		T23	13
valid_sources[0x28]	113313	1			T19	2		T20	3		T22	5
valid_sources[0x29]	55576	1			T19	3		T20	12		T23	10
valid_sources[0x2a]	59285	1			T20	5		T22	1		T23	23
valid_sources[0x2b]	56839	1			T20	8		T23	16		T2	323
valid_sources[0x2c]	58972	1			T20	10		T23	9		T2	309
valid_sources[0x2d]	60210	1			T20	2		T22	1		T23	13
valid_sources[0x2e]	55138	1			T20	4		T22	1		T23	14
valid_sources[0x2f]	58368	1			T18	2		T20	5		T22	1
valid_sources[0x30]	58914	1			T18	1		T19	5		T20	12
valid_sources[0x31]	57935	1			T18	1		T20	17		T23	12
valid_sources[0x32]	57103	1			T18	1		T20	12		T23	16
valid_sources[0x33]	59607	1			T18	1		T19	2		T20	8
valid_sources[0x34]	56540	1			T20	5		T22	5		T23	19
valid_sources[0x35]	58311	1			T20	8		T23	15		T2	293
valid_sources[0x36]	61704	1			T20	7		T23	15		T2	297
valid_sources[0x37]	155197	1			T20	11		T22	2		T23	13
valid_sources[0x38]	50778	1			T20	15		T22	1		T23	22
valid_sources[0x39]	62282	1			T20	6		T22	1		T23	7
valid_sources[0x3a]	62557	1			T18	1		T20	10		T22	1
valid_sources[0x3b]	58275	1			T20	11		T22	5		T23	12
valid_sources[0x3c]	58401	1			T19	4		T20	5		T22	2
valid_sources[0x3d]	56745	1			T18	1		T20	7		T22	1
valid_sources[0x3e]	51374	1			T18	2		T20	15		T23	13
valid_sources[0x3f]	57686	1			T19	2		T20	12		T22	3
valid_sources[0x40]	61785	1			T20	10		T22	1		T23	8
valid_sources[0x41]	61565	1			T20	8		T22	2		T23	12
valid_sources[0x42]	64706	1			T20	7		T21	3		T22	1
valid_sources[0x43]	59516	1			T19	4		T20	5		T22	1
valid_sources[0x44]	55192	1			T20	6		T23	10		T2	332
valid_sources[0x45]	57149	1			T20	3		T22	1		T23	15
valid_sources[0x46]	63303	1			T18	2		T20	8		T22	3
valid_sources[0x47]	54855	1			T20	9		T22	2		T23	9
valid_sources[0x48]	55152	1			T20	14		T22	2		T23	16
valid_sources[0x49]	57027	1			T20	3		T22	1		T23	18
valid_sources[0x4a]	58168	1			T18	1		T20	5		T22	2
valid_sources[0x4b]	53861	1			T18	1		T20	9		T23	7
valid_sources[0x4c]	59938	1			T20	8		T22	1		T23	12
valid_sources[0x4d]	63592	1			T20	5		T22	1		T23	18
valid_sources[0x4e]	70301	1			T18	1		T20	5		T22	2
valid_sources[0x4f]	58519	1			T18	1		T20	5		T23	8
valid_sources[0x50]	57924	1			T20	1		T22	1		T23	10
valid_sources[0x51]	59159	1			T18	1		T20	5		T23	14
valid_sources[0x52]	60446	1			T20	13		T22	2		T23	9
valid_sources[0x53]	57280	1			T20	13		T22	1		T23	15
valid_sources[0x54]	57457	1			T18	1		T20	10		T22	1
valid_sources[0x55]	58298	1			T20	6		T22	2		T23	6
valid_sources[0x56]	60210	1			T20	9		T23	15		T2	292
valid_sources[0x57]	52600	1			T20	11		T22	2		T23	14
valid_sources[0x58]	199472	1			T20	7		T23	5		T2	337
valid_sources[0x59]	57536	1			T20	9		T22	1		T23	13
valid_sources[0x5a]	51705	1			T20	10		T23	4		T2	314
valid_sources[0x5b]	61179	1			T18	2		T20	6		T22	1
valid_sources[0x5c]	53827	1			T18	1		T20	13		T21	1
valid_sources[0x5d]	50052	1			T18	2		T20	3		T22	1
valid_sources[0x5e]	188760	1			T20	10		T21	1		T22	1
valid_sources[0x5f]	67121	1			T18	1		T20	2		T22	2
valid_sources[0x60]	57949	1			T18	2		T20	9		T22	2
valid_sources[0x61]	58196	1			T19	4		T20	9		T22	2
valid_sources[0x62]	52206	1			T18	2		T20	6		T23	13
valid_sources[0x63]	60570	1			T20	13		T21	1		T22	2
valid_sources[0x64]	54662	1			T20	6		T22	1		T23	8
valid_sources[0x65]	66975	1			T18	1		T19	1		T20	3
valid_sources[0x66]	51907	1			T18	1		T19	1		T20	5
valid_sources[0x67]	55273	1			T20	12		T22	2		T23	13
valid_sources[0x68]	63373	1			T20	6		T22	2		T23	11
valid_sources[0x69]	59113	1			T20	16		T22	3		T23	8
valid_sources[0x6a]	71212	1			T18	1		T19	6		T20	6
valid_sources[0x6b]	57761	1			T18	1		T20	7		T22	2
valid_sources[0x6c]	65381	1			T20	5		T23	14		T2	305
valid_sources[0x6d]	56181	1			T20	8		T22	1		T23	8
valid_sources[0x6e]	138952	1			T20	9		T22	2		T23	18
valid_sources[0x6f]	51844	1			T18	2		T20	7		T23	14
valid_sources[0x70]	55241	1			T20	9		T22	1		T23	10
valid_sources[0x71]	59259	1			T19	1		T20	4		T22	1
valid_sources[0x72]	59496	1			T18	1		T20	7		T23	23
valid_sources[0x73]	58040	1			T20	8		T22	1		T23	16
valid_sources[0x74]	60392	1			T20	5		T22	2		T23	10
valid_sources[0x75]	57485	1			T20	13		T22	1		T23	18
valid_sources[0x76]	61898	1			T20	5		T22	2		T23	9
valid_sources[0x77]	59846	1			T18	3		T20	10		T22	1
valid_sources[0x78]	62133	1			T19	13		T20	13		T22	2
valid_sources[0x79]	60456	1			T20	14		T23	21		T2	288
valid_sources[0x7a]	48127	1			T20	7		T22	4		T23	12
valid_sources[0x7b]	59443	1			T18	1		T20	7		T22	2
valid_sources[0x7c]	57032	1			T19	4		T20	10		T21	1
valid_sources[0x7d]	56942	1			T20	13		T22	2		T23	18
valid_sources[0x7e]	58667	1			T20	10		T21	1		T22	2
valid_sources[0x7f]	54154	1			T20	7		T23	9		T2	319
valid_sources[0x80]	59230	1			T20	10		T22	1		T23	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3768255

1

T18

10

T19

9

T20

785

values[0x0]

all_enables

biggest_size

4796176

1

T18

37

T19

52

T20

265

values[0x1]

all_enables

biggest_size

4796486

1

T18

34

T19

44

T20

246