Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	122114149	0	0	0
ctrl_en_input_filter_rd_A	122114149	50636	0	0
intr_ctrl_en_falling_rd_A	122114149	51157	0	0
intr_ctrl_en_lvlhigh_rd_A	122114149	51490	0	0
intr_ctrl_en_lvllow_rd_A	122114149	50936	0	0
intr_ctrl_en_rising_rd_A	122114149	52095	0	0
intr_enable_rd_A	122114149	52024	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122114149	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122114149	50636	0	0
T1	10749	50	0	0
T2	844444	3001	0	0
T3	36564	162	0	0
T4	0	357	0	0
T5	0	3900	0	0
T6	0	4017	0	0
T7	0	1894	0	0
T8	0	113	0	0
T9	0	3214	0	0
T10	0	125	0	0
T11	36870	0	0	0
T12	79582	0	0	0
T13	5402	0	0	0
T14	24060	0	0	0
T15	3409	0	0	0
T16	3789	0	0	0
T17	3325	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122114149	51157	0	0
T1	10749	54	0	0
T2	844444	3013	0	0
T3	36564	151	0	0
T4	0	301	0	0
T5	0	3979	0	0
T6	0	4038	0	0
T7	0	2015	0	0
T8	0	209	0	0
T9	0	3128	0	0
T10	0	150	0	0
T11	36870	0	0	0
T12	79582	0	0	0
T13	5402	0	0	0
T14	24060	0	0	0
T15	3409	0	0	0
T16	3789	0	0	0
T17	3325	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122114149	51490	0	0
T1	10749	38	0	0
T2	844444	2913	0	0
T3	36564	171	0	0
T4	0	329	0	0
T5	0	3859	0	0
T6	0	4127	0	0
T7	0	2236	0	0
T8	0	205	0	0
T9	0	3631	0	0
T10	0	158	0	0
T11	36870	0	0	0
T12	79582	0	0	0
T13	5402	0	0	0
T14	24060	0	0	0
T15	3409	0	0	0
T16	3789	0	0	0
T17	3325	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122114149	50936	0	0
T1	10749	62	0	0
T2	844444	2826	0	0
T3	36564	174	0	0
T4	0	373	0	0
T5	0	4170	0	0
T6	0	4171	0	0
T7	0	2257	0	0
T8	0	168	0	0
T9	0	3433	0	0
T10	0	181	0	0
T11	36870	0	0	0
T12	79582	0	0	0
T13	5402	0	0	0
T14	24060	0	0	0
T15	3409	0	0	0
T16	3789	0	0	0
T17	3325	0	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122114149	52095	0	0
T1	10749	74	0	0
T2	844444	2979	0	0
T3	36564	207	0	0
T4	0	332	0	0
T5	0	3996	0	0
T6	0	3887	0	0
T7	0	2049	0	0
T8	0	157	0	0
T9	0	3457	0	0
T10	0	118	0	0
T11	36870	0	0	0
T12	79582	0	0	0
T13	5402	0	0	0
T14	24060	0	0	0
T15	3409	0	0	0
T16	3789	0	0	0
T17	3325	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122114149	52024	0	0
T1	10749	45	0	0
T2	844444	3123	0	0
T3	36564	172	0	0
T4	0	274	0	0
T5	0	4150	0	0
T6	0	4100	0	0
T7	0	2085	0	0
T8	0	161	0	0
T9	0	3337	0	0
T10	0	106	0	0
T11	36870	0	0	0
T12	79582	0	0	0
T13	5402	0	0	0
T14	24060	0	0	0
T15	3409	0	0	0
T16	3789	0	0	0
T17	3325	0	0	0