Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3760314	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

17384186

1

T24

712

T25

104

T26

1027

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8323178	1			T24	810		T25	70		T26	632
values[0x0]	6291489	1			T24	154		T25	37		T26	382
values[0x1]	6529833	1			T24	137		T25	34		T26	338

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2871271	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

18273229

1

T24

782

T25

114

T26

1097

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	84022	1			T24	5		T26	6		T1	4
valid_sources[0x01]	75315	1			T24	8		T26	6		T12	4
valid_sources[0x02]	78050	1			T24	5		T26	3		T1	9
valid_sources[0x03]	77688	1			T24	9		T26	5		T1	9
valid_sources[0x04]	73060	1			T24	2		T26	3		T1	31
valid_sources[0x05]	74962	1			T24	2		T26	2		T1	29
valid_sources[0x06]	73298	1			T24	4		T26	7		T1	6
valid_sources[0x07]	75006	1			T24	3		T26	9		T1	13
valid_sources[0x08]	77072	1			T24	5		T26	14		T1	14
valid_sources[0x09]	85793	1			T24	3		T26	10		T1	3
valid_sources[0x0a]	157140	1			T24	2		T26	15		T1	4
valid_sources[0x0b]	77389	1			T24	2		T26	8		T1	3
valid_sources[0x0c]	75819	1			T24	3		T26	2		T1	12
valid_sources[0x0d]	71762	1			T24	1		T26	6		T1	2
valid_sources[0x0e]	78951	1			T24	5		T26	3		T1	7
valid_sources[0x0f]	77595	1			T24	1		T26	5		T1	27
valid_sources[0x10]	193343	1			T24	6		T26	4		T1	1
valid_sources[0x11]	223871	1			T26	5		T12	2		T14	1
valid_sources[0x12]	79892	1			T24	17		T26	2		T1	49
valid_sources[0x13]	78910	1			T24	1		T26	3		T12	4
valid_sources[0x14]	75826	1			T26	1		T1	14		T12	1
valid_sources[0x15]	74410	1			T24	1		T26	1		T1	30
valid_sources[0x16]	85117	1			T24	6		T26	7		T1	9
valid_sources[0x17]	78194	1			T24	4		T26	8		T1	2
valid_sources[0x18]	81204	1			T24	2		T26	6		T1	24
valid_sources[0x19]	72199	1			T24	5		T26	7		T12	5
valid_sources[0x1a]	75897	1			T24	3		T26	9		T12	1
valid_sources[0x1b]	79410	1			T24	5		T26	3		T1	28
valid_sources[0x1c]	74426	1			T24	2		T26	5		T1	18
valid_sources[0x1d]	86150	1			T24	2		T26	6		T1	20
valid_sources[0x1e]	80083	1			T24	7		T26	9		T1	12
valid_sources[0x1f]	68285	1			T24	8		T26	7		T1	6
valid_sources[0x20]	77325	1			T24	2		T26	4		T1	14
valid_sources[0x21]	77614	1			T24	1		T26	2		T1	4
valid_sources[0x22]	77567	1			T24	2		T26	3		T1	23
valid_sources[0x23]	77431	1			T24	6		T26	8		T1	9
valid_sources[0x24]	80734	1			T24	13		T26	6		T1	15
valid_sources[0x25]	76716	1			T24	4		T26	1		T1	4
valid_sources[0x26]	76615	1			T24	4		T26	1		T1	8
valid_sources[0x27]	73115	1			T24	3		T26	4		T1	30
valid_sources[0x28]	114247	1			T24	13		T1	13		T12	2
valid_sources[0x29]	82530	1			T26	6		T1	9		T12	2
valid_sources[0x2a]	74867	1			T24	3		T26	2		T1	1
valid_sources[0x2b]	77322	1			T24	7		T26	6		T1	3
valid_sources[0x2c]	74870	1			T24	4		T26	13		T1	20
valid_sources[0x2d]	78963	1			T24	3		T26	3		T1	14
valid_sources[0x2e]	76209	1			T24	1		T26	5		T1	4
valid_sources[0x2f]	78655	1			T24	2		T26	6		T1	14
valid_sources[0x30]	78118	1			T24	4		T26	6		T1	13
valid_sources[0x31]	80316	1			T24	4		T26	1		T1	15
valid_sources[0x32]	74146	1			T26	7		T1	55		T12	3
valid_sources[0x33]	82595	1			T24	3		T26	9		T1	5
valid_sources[0x34]	77315	1			T24	3		T26	2		T1	3
valid_sources[0x35]	72297	1			T26	2		T1	9		T12	2
valid_sources[0x36]	77762	1			T24	5		T26	6		T1	16
valid_sources[0x37]	87520	1			T24	4		T1	3		T16	2
valid_sources[0x38]	74358	1			T24	9		T1	1		T16	2
valid_sources[0x39]	78285	1			T24	2		T1	6		T12	2
valid_sources[0x3a]	79406	1			T24	9		T26	6		T1	8
valid_sources[0x3b]	77172	1			T24	3		T26	10		T1	15
valid_sources[0x3c]	88353	1			T24	6		T26	4		T1	22
valid_sources[0x3d]	76703	1			T24	5		T26	4		T1	38
valid_sources[0x3e]	70170	1			T24	9		T26	13		T1	16
valid_sources[0x3f]	78906	1			T24	1		T26	3		T1	1
valid_sources[0x40]	76642	1			T26	5		T1	27		T12	3
valid_sources[0x41]	82738	1			T24	3		T26	1		T1	35
valid_sources[0x42]	82031	1			T24	2		T26	5		T1	14
valid_sources[0x43]	76688	1			T24	3		T26	3		T1	3
valid_sources[0x44]	78714	1			T24	2		T1	1		T12	1
valid_sources[0x45]	77966	1			T24	5		T26	13		T1	15
valid_sources[0x46]	72259	1			T24	1		T26	2		T16	2
valid_sources[0x47]	82504	1			T24	2		T26	14		T1	1
valid_sources[0x48]	76693	1			T24	21		T26	6		T1	48
valid_sources[0x49]	77143	1			T24	3		T26	2		T1	12
valid_sources[0x4a]	87272	1			T24	2		T26	1		T1	3
valid_sources[0x4b]	78303	1			T24	3		T26	10		T1	13
valid_sources[0x4c]	70787	1			T24	2		T26	1		T1	2
valid_sources[0x4d]	76446	1			T24	6		T26	5		T1	10
valid_sources[0x4e]	76316	1			T24	4		T26	3		T1	21
valid_sources[0x4f]	80667	1			T24	10		T26	10		T1	5
valid_sources[0x50]	150920	1			T24	12		T26	4		T12	3
valid_sources[0x51]	86322	1			T24	3		T26	1		T1	20
valid_sources[0x52]	78533	1			T24	4		T26	2		T1	15
valid_sources[0x53]	77714	1			T24	4		T26	4		T1	27
valid_sources[0x54]	83541	1			T24	7		T26	5		T1	14
valid_sources[0x55]	71757	1			T24	2		T26	2		T1	1
valid_sources[0x56]	73863	1			T26	4		T1	18		T12	3
valid_sources[0x57]	83151	1			T24	4		T26	4		T12	3
valid_sources[0x58]	82710	1			T24	5		T26	9		T1	4
valid_sources[0x59]	74889	1			T24	6		T26	7		T1	7
valid_sources[0x5a]	86002	1			T24	7		T26	1		T1	9
valid_sources[0x5b]	81045	1			T24	7		T26	1		T1	1
valid_sources[0x5c]	172458	1			T24	3		T26	1		T1	9
valid_sources[0x5d]	71009	1			T24	7		T26	1		T1	22
valid_sources[0x5e]	79055	1			T24	3		T26	1		T1	19
valid_sources[0x5f]	86765	1			T24	4		T26	2		T1	18
valid_sources[0x60]	78788	1			T24	6		T26	6		T1	18
valid_sources[0x61]	74170	1			T24	3		T26	5		T1	4
valid_sources[0x62]	79617	1			T24	9		T26	14		T1	1
valid_sources[0x63]	73635	1			T24	6		T26	4		T1	36
valid_sources[0x64]	72801	1			T24	3		T26	12		T1	31
valid_sources[0x65]	78687	1			T24	5		T26	4		T1	16
valid_sources[0x66]	77206	1			T24	6		T26	3		T12	2
valid_sources[0x67]	80389	1			T24	12		T26	4		T1	12
valid_sources[0x68]	82666	1			T24	2		T12	2		T16	1
valid_sources[0x69]	81082	1			T24	2		T1	18		T12	2
valid_sources[0x6a]	79269	1			T24	6		T26	2		T1	9
valid_sources[0x6b]	78911	1			T24	4		T26	3		T1	20
valid_sources[0x6c]	85362	1			T24	2		T26	1		T1	38
valid_sources[0x6d]	79963	1			T24	2		T26	9		T1	14
valid_sources[0x6e]	77454	1			T24	8		T26	8		T1	15
valid_sources[0x6f]	80344	1			T24	5		T26	8		T1	46
valid_sources[0x70]	78569	1			T24	4		T26	6		T1	2
valid_sources[0x71]	80809	1			T24	4		T26	2		T12	1
valid_sources[0x72]	70898	1			T24	6		T26	6		T1	27
valid_sources[0x73]	81874	1			T24	9		T26	19		T1	23
valid_sources[0x74]	78524	1			T24	6		T26	6		T1	2
valid_sources[0x75]	76158	1			T24	1		T26	7		T1	30
valid_sources[0x76]	80292	1			T24	7		T26	3		T1	1
valid_sources[0x77]	84901	1			T24	3		T26	9		T12	1
valid_sources[0x78]	74226	1			T24	1		T26	7		T1	12
valid_sources[0x79]	77566	1			T24	13		T26	6		T1	26
valid_sources[0x7a]	81307	1			T24	2		T26	1		T1	6
valid_sources[0x7b]	76480	1			T24	6		T26	11		T1	9
valid_sources[0x7c]	79563	1			T24	1		T26	1		T1	11
valid_sources[0x7d]	81754	1			T24	9		T26	8		T1	2
valid_sources[0x7e]	82053	1			T24	2		T26	26		T1	20
valid_sources[0x7f]	153578	1			T24	16		T26	5		T1	2
valid_sources[0x80]	79438	1			T24	9		T26	1		T1	17

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4856600

1

T24

421

T25

33

T26

307

values[0x0]

all_enables

biggest_size

6267118

1

T24

154

T25

37

T26

382

values[0x1]

all_enables

biggest_size

6260468

1

T24

137

T25

34

T26

338