Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3493442	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

16252419

1

T23

256

T24

2405

T25

409

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7748076	1			T23	19		T24	3764		T25	90
values[0x0]	5885422	1			T23	132		T24	302		T25	183
values[0x1]	6112363	1			T23	114		T24	249		T25	185

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2664597	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

17081264

1

T23

260

T24

2808

T25

424

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	72756	1			T23	1		T25	2		T26	4
valid_sources[0x01]	179135	1			T25	1		T26	1		T27	340
valid_sources[0x02]	74594	1			T27	343		T28	10		T30	1
valid_sources[0x03]	71340	1			T23	2		T25	3		T27	352
valid_sources[0x04]	73803	1			T23	3		T25	7		T27	305
valid_sources[0x05]	76625	1			T25	2		T26	1		T27	315
valid_sources[0x06]	73052	1			T23	2		T25	2		T27	327
valid_sources[0x07]	67672	1			T25	2		T26	1		T27	345
valid_sources[0x08]	70155	1			T23	1		T25	4		T26	2
valid_sources[0x09]	70372	1			T23	1		T25	3		T27	307
valid_sources[0x0a]	75054	1			T25	3		T27	326		T28	2
valid_sources[0x0b]	73893	1			T25	1		T26	1		T27	321
valid_sources[0x0c]	77666	1			T23	3		T26	1		T27	287
valid_sources[0x0d]	73135	1			T26	3		T27	367		T28	4
valid_sources[0x0e]	77026	1			T23	1		T25	1		T27	332
valid_sources[0x0f]	147152	1			T23	1		T25	1		T26	2
valid_sources[0x10]	72794	1			T23	1		T25	1		T27	316
valid_sources[0x11]	67896	1			T26	2		T27	324		T28	1
valid_sources[0x12]	72443	1			T23	3		T25	2		T26	1
valid_sources[0x13]	70385	1			T23	1		T25	2		T26	2
valid_sources[0x14]	80613	1			T25	2		T27	314		T28	8
valid_sources[0x15]	69862	1			T23	1		T25	5		T27	294
valid_sources[0x16]	120434	1			T26	1		T27	323		T28	12
valid_sources[0x17]	78244	1			T23	2		T25	4		T26	1
valid_sources[0x18]	67567	1			T25	2		T26	1		T27	328
valid_sources[0x19]	70254	1			T25	1		T26	1		T27	311
valid_sources[0x1a]	71485	1			T23	1		T25	2		T27	309
valid_sources[0x1b]	75027	1			T25	2		T26	1		T27	349
valid_sources[0x1c]	83947	1			T23	1		T25	3		T27	292
valid_sources[0x1d]	73961	1			T23	2		T25	1		T27	317
valid_sources[0x1e]	75283	1			T23	2		T25	2		T27	343
valid_sources[0x1f]	71642	1			T23	1		T25	4		T27	298
valid_sources[0x20]	75173	1			T23	3		T27	329		T28	4
valid_sources[0x21]	73376	1			T25	6		T27	283		T28	3
valid_sources[0x22]	70421	1			T25	3		T27	343		T28	5
valid_sources[0x23]	145998	1			T23	1		T25	1		T26	1
valid_sources[0x24]	69967	1			T25	4		T27	317		T28	2
valid_sources[0x25]	69714	1			T25	6		T26	1		T27	307
valid_sources[0x26]	71174	1			T23	3		T27	304		T28	2
valid_sources[0x27]	71316	1			T27	328		T28	5		T29	5
valid_sources[0x28]	70339	1			T23	1		T25	1		T27	289
valid_sources[0x29]	75537	1			T23	2		T25	1		T27	307
valid_sources[0x2a]	73043	1			T27	299		T28	4		T29	1
valid_sources[0x2b]	139493	1			T23	2		T25	2		T27	320
valid_sources[0x2c]	73584	1			T27	321		T28	1		T31	1225
valid_sources[0x2d]	71872	1			T25	2		T26	4		T27	350
valid_sources[0x2e]	70242	1			T27	348		T28	2		T29	3
valid_sources[0x2f]	70024	1			T23	1		T27	316		T28	11
valid_sources[0x30]	75784	1			T25	1		T26	1		T27	285
valid_sources[0x31]	79271	1			T23	1		T25	2		T26	1
valid_sources[0x32]	147142	1			T23	1		T25	3		T26	1
valid_sources[0x33]	77232	1			T23	1		T25	4		T26	1
valid_sources[0x34]	71464	1			T23	1		T26	2		T27	304
valid_sources[0x35]	69979	1			T25	1		T26	3		T27	311
valid_sources[0x36]	68119	1			T25	3		T26	1		T27	332
valid_sources[0x37]	76408	1			T25	1		T26	1		T27	367
valid_sources[0x38]	71817	1			T23	2		T25	1		T26	2
valid_sources[0x39]	74843	1			T23	1		T25	4		T27	345
valid_sources[0x3a]	70198	1			T25	3		T26	1		T27	334
valid_sources[0x3b]	74451	1			T23	1		T25	4		T26	1
valid_sources[0x3c]	73355	1			T23	3		T27	319		T28	2
valid_sources[0x3d]	69451	1			T23	1		T26	3		T27	286
valid_sources[0x3e]	68446	1			T25	6		T26	2		T27	338
valid_sources[0x3f]	76041	1			T25	1		T27	335		T28	4
valid_sources[0x40]	82493	1			T24	4315		T25	1		T27	342
valid_sources[0x41]	75984	1			T25	1		T26	4		T27	320
valid_sources[0x42]	75253	1			T27	317		T28	4		T29	1
valid_sources[0x43]	68076	1			T25	2		T26	1		T27	296
valid_sources[0x44]	78301	1			T27	317		T28	1		T29	3
valid_sources[0x45]	71142	1			T23	2		T25	6		T26	2
valid_sources[0x46]	73850	1			T25	3		T27	363		T28	8
valid_sources[0x47]	76087	1			T25	1		T27	344		T28	3
valid_sources[0x48]	70475	1			T25	2		T26	3		T27	321
valid_sources[0x49]	73092	1			T25	1		T26	3		T27	315
valid_sources[0x4a]	74455	1			T23	1		T27	309		T28	7
valid_sources[0x4b]	69452	1			T23	1		T26	1		T27	291
valid_sources[0x4c]	70488	1			T23	5		T26	2		T27	306
valid_sources[0x4d]	77214	1			T26	1		T27	342		T28	3
valid_sources[0x4e]	68537	1			T23	3		T25	1		T26	2
valid_sources[0x4f]	73253	1			T23	1		T25	2		T27	299
valid_sources[0x50]	74764	1			T23	3		T25	2		T26	2
valid_sources[0x51]	79637	1			T23	1		T25	2		T26	1
valid_sources[0x52]	71648	1			T25	1		T27	345		T28	6
valid_sources[0x53]	69696	1			T25	1		T27	284		T28	5
valid_sources[0x54]	71197	1			T26	5		T27	312		T30	5
valid_sources[0x55]	68506	1			T23	1		T27	314		T28	4
valid_sources[0x56]	71977	1			T25	1		T26	3		T27	364
valid_sources[0x57]	70989	1			T23	2		T25	1		T26	1
valid_sources[0x58]	73013	1			T23	1		T25	1		T26	3
valid_sources[0x59]	72925	1			T25	2		T26	1		T27	311
valid_sources[0x5a]	71943	1			T25	3		T26	3		T27	336
valid_sources[0x5b]	71335	1			T25	3		T26	2		T27	323
valid_sources[0x5c]	71660	1			T23	3		T25	4		T26	1
valid_sources[0x5d]	73758	1			T25	1		T27	308		T28	6
valid_sources[0x5e]	72260	1			T25	4		T27	322		T28	1
valid_sources[0x5f]	73419	1			T25	2		T27	346		T28	5
valid_sources[0x60]	68258	1			T23	1		T25	1		T26	1
valid_sources[0x61]	69058	1			T23	1		T25	1		T26	3
valid_sources[0x62]	69207	1			T27	310		T29	1		T31	943
valid_sources[0x63]	72368	1			T23	4		T25	5		T27	305
valid_sources[0x64]	77018	1			T23	1		T25	1		T27	299
valid_sources[0x65]	77602	1			T23	2		T25	2		T27	305
valid_sources[0x66]	70102	1			T23	1		T27	341		T28	3
valid_sources[0x67]	72577	1			T25	2		T26	2		T27	329
valid_sources[0x68]	78701	1			T23	2		T25	1		T26	1
valid_sources[0x69]	76271	1			T23	1		T26	1		T27	360
valid_sources[0x6a]	69427	1			T23	6		T25	2		T26	1
valid_sources[0x6b]	69803	1			T27	281		T28	2		T29	1
valid_sources[0x6c]	73952	1			T23	2		T25	2		T26	2
valid_sources[0x6d]	73211	1			T23	1		T25	2		T26	1
valid_sources[0x6e]	72316	1			T23	1		T25	1		T27	287
valid_sources[0x6f]	73298	1			T23	4		T25	1		T26	1
valid_sources[0x70]	75659	1			T26	1		T27	316		T28	5
valid_sources[0x71]	72114	1			T27	334		T28	6		T29	2
valid_sources[0x72]	73115	1			T26	6		T27	319		T28	11
valid_sources[0x73]	70042	1			T27	340		T28	3		T29	1
valid_sources[0x74]	68689	1			T23	1		T27	339		T28	6
valid_sources[0x75]	71441	1			T23	1		T25	2		T26	2
valid_sources[0x76]	70240	1			T26	1		T27	325		T28	1
valid_sources[0x77]	78774	1			T25	1		T26	1		T27	287
valid_sources[0x78]	69585	1			T23	3		T25	1		T27	310
valid_sources[0x79]	72463	1			T25	1		T27	320		T28	8
valid_sources[0x7a]	77560	1			T23	2		T25	2		T26	2
valid_sources[0x7b]	74536	1			T25	1		T26	2		T27	341
valid_sources[0x7c]	71104	1			T25	5		T27	319		T28	12
valid_sources[0x7d]	74991	1			T25	2		T26	2		T27	317
valid_sources[0x7e]	80332	1			T25	3		T26	1		T27	317
valid_sources[0x7f]	83918	1			T23	3		T26	2		T27	331
valid_sources[0x80]	68372	1			T23	3		T25	3		T26	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4536146

1

T23

10

T24

1854

T25

41

values[0x0]

all_enables

biggest_size

5861942

1

T23

132

T24

302

T25

183

values[0x1]

all_enables

biggest_size

5854331

1

T23

114

T24

249

T25

185