Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	180804697	0	0	0
ctrl_en_input_filter_rd_A	180804697	82767	0	0
intr_ctrl_en_falling_rd_A	180804697	86048	0	0
intr_ctrl_en_lvlhigh_rd_A	180804697	83376	0	0
intr_ctrl_en_lvllow_rd_A	180804697	86434	0	0
intr_ctrl_en_rising_rd_A	180804697	81679	0	0
intr_enable_rd_A	180804697	83270	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180804697	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180804697	82767	0	0
T1	140376	4264	0	0
T2	13399	60	0	0
T3	0	27832	0	0
T4	0	5282	0	0
T5	0	8069	0	0
T6	0	173	0	0
T7	0	273	0	0
T8	0	2	0	0
T9	0	9	0	0
T10	0	398	0	0
T11	3637	0	0	0
T12	4525	0	0	0
T13	3102	0	0	0
T14	2205	0	0	0
T15	4318	0	0	0
T16	3964	0	0	0
T17	2918	0	0	0
T18	9092	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180804697	86048	0	0
T1	140376	4273	0	0
T2	13399	46	0	0
T3	0	30034	0	0
T4	0	5169	0	0
T5	0	8004	0	0
T6	0	170	0	0
T7	0	213	0	0
T10	0	416	0	0
T11	3637	0	0	0
T12	4525	0	0	0
T13	3102	0	0	0
T14	2205	0	0	0
T15	4318	0	0	0
T16	3964	0	0	0
T17	2918	0	0	0
T18	9092	0	0	0
T19	0	5	0	0
T20	0	138	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180804697	83376	0	0
T1	140376	4003	0	0
T2	13399	85	0	0
T3	0	27206	0	0
T4	0	5325	0	0
T5	0	8133	0	0
T6	0	172	0	0
T7	0	243	0	0
T9	0	4	0	0
T10	0	380	0	0
T11	3637	0	0	0
T12	4525	0	0	0
T13	3102	0	0	0
T14	2205	0	0	0
T15	4318	0	0	0
T16	3964	0	0	0
T17	2918	0	0	0
T18	9092	0	0	0
T21	0	1	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180804697	86434	0	0
T1	140376	3850	0	0
T2	13399	90	0	0
T3	0	30663	0	0
T4	0	5079	0	0
T5	0	7855	0	0
T6	0	164	0	0
T7	0	244	0	0
T8	0	2	0	0
T9	0	6	0	0
T11	3637	0	0	0
T12	4525	0	0	0
T13	3102	0	0	0
T14	2205	0	0	0
T15	4318	0	0	0
T16	3964	0	0	0
T17	2918	0	0	0
T18	9092	0	0	0
T21	0	7	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180804697	81679	0	0
T1	140376	3856	0	0
T2	13399	66	0	0
T3	0	27248	0	0
T4	0	4853	0	0
T5	0	7889	0	0
T6	0	171	0	0
T7	0	311	0	0
T8	0	3	0	0
T9	0	6	0	0
T11	3637	0	0	0
T12	4525	0	0	0
T13	3102	0	0	0
T14	2205	0	0	0
T15	4318	0	0	0
T16	3964	0	0	0
T17	2918	0	0	0
T18	9092	0	0	0
T19	0	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180804697	83270	0	0
T1	140376	3933	0	0
T2	13399	57	0	0
T3	0	26654	0	0
T4	0	5331	0	0
T5	0	8129	0	0
T6	0	205	0	0
T7	0	241	0	0
T8	0	12	0	0
T10	0	424	0	0
T11	3637	0	0	0
T12	4525	0	0	0
T13	3102	0	0	0
T14	2205	0	0	0
T15	4318	0	0	0
T16	3964	0	0	0
T17	2918	0	0	0
T18	9092	0	0	0
T22	0	2	0	0