Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3541810	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

15670246

1

T32

123656

T33

895

T34

163

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7712798	1			T32	70738		T33	1107		T34	70
values[0x0]	5651683	1			T32	44404		T33	184		T34	62
values[0x1]	5847575	1			T32	43860		T33	158		T34	66

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2728004	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

16484052

1

T32

130719

T33

985

T34

170

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	182894	1			T32	612		T33	5		T24	5
valid_sources[0x01]	68109	1			T32	648		T33	2		T34	3
valid_sources[0x02]	151768	1			T32	631		T33	7		T35	4
valid_sources[0x03]	85295	1			T32	676		T33	5		T35	5
valid_sources[0x04]	75044	1			T32	588		T33	2		T36	11
valid_sources[0x05]	70682	1			T32	630		T33	10		T35	2
valid_sources[0x06]	79892	1			T32	646		T33	13		T36	20
valid_sources[0x07]	70353	1			T32	603		T33	1		T34	1
valid_sources[0x08]	69635	1			T32	645		T33	3		T35	1
valid_sources[0x09]	67550	1			T32	641		T33	7		T34	1
valid_sources[0x0a]	64921	1			T32	606		T33	6		T34	1
valid_sources[0x0b]	71872	1			T32	620		T33	4		T34	2
valid_sources[0x0c]	70714	1			T32	592		T33	7		T34	3
valid_sources[0x0d]	70920	1			T32	637		T33	2		T35	5
valid_sources[0x0e]	69392	1			T32	632		T33	10		T34	2
valid_sources[0x0f]	70518	1			T32	627		T33	6		T24	23
valid_sources[0x10]	75001	1			T32	570		T33	5		T35	5
valid_sources[0x11]	71683	1			T32	647		T33	7		T34	2
valid_sources[0x12]	68155	1			T32	605		T35	4		T23	1
valid_sources[0x13]	70253	1			T32	550		T33	5		T34	3
valid_sources[0x14]	71255	1			T32	644		T33	7		T34	4
valid_sources[0x15]	194089	1			T32	617		T33	3		T34	1
valid_sources[0x16]	74403	1			T32	611		T33	4		T34	3
valid_sources[0x17]	67618	1			T32	586		T33	10		T23	1
valid_sources[0x18]	70460	1			T32	578		T33	3		T35	2
valid_sources[0x19]	126775	1			T32	606		T33	9		T34	1
valid_sources[0x1a]	70208	1			T32	648		T33	7		T24	20
valid_sources[0x1b]	71408	1			T32	578		T33	3		T34	3
valid_sources[0x1c]	71844	1			T32	663		T33	8		T34	1
valid_sources[0x1d]	69835	1			T32	706		T33	11		T35	2
valid_sources[0x1e]	64881	1			T32	625		T33	3		T34	1
valid_sources[0x1f]	67425	1			T32	613		T33	4		T36	6
valid_sources[0x20]	70360	1			T32	580		T33	6		T34	1
valid_sources[0x21]	71549	1			T32	618		T33	1		T34	4
valid_sources[0x22]	67164	1			T32	647		T33	3		T34	1
valid_sources[0x23]	70477	1			T32	621		T33	6		T34	3
valid_sources[0x24]	75947	1			T32	627		T33	6		T34	1
valid_sources[0x25]	73383	1			T32	641		T33	2		T35	3
valid_sources[0x26]	72846	1			T32	604		T33	7		T36	22
valid_sources[0x27]	67818	1			T32	519		T33	6		T36	21
valid_sources[0x28]	168405	1			T32	668		T33	11		T34	1
valid_sources[0x29]	66273	1			T32	643		T33	2		T34	2
valid_sources[0x2a]	72435	1			T32	626		T33	5		T34	6
valid_sources[0x2b]	65459	1			T32	624		T33	6		T34	2
valid_sources[0x2c]	63755	1			T32	641		T33	12		T36	11
valid_sources[0x2d]	66260	1			T32	620		T33	10		T35	2
valid_sources[0x2e]	67419	1			T32	624		T33	5		T34	4
valid_sources[0x2f]	68753	1			T32	550		T33	9		T35	4
valid_sources[0x30]	68648	1			T32	569		T33	6		T35	2
valid_sources[0x31]	69230	1			T32	658		T33	10		T35	1
valid_sources[0x32]	73074	1			T32	626		T33	6		T35	4
valid_sources[0x33]	69369	1			T32	665		T33	5		T35	1
valid_sources[0x34]	71035	1			T32	631		T33	6		T35	3
valid_sources[0x35]	70991	1			T32	610		T33	12		T34	1
valid_sources[0x36]	68218	1			T32	622		T33	14		T36	1
valid_sources[0x37]	70818	1			T32	571		T33	6		T24	23
valid_sources[0x38]	73162	1			T32	594		T33	14		T34	1
valid_sources[0x39]	74940	1			T32	607		T33	9		T35	1
valid_sources[0x3a]	69018	1			T32	635		T33	4		T35	2
valid_sources[0x3b]	64689	1			T32	621		T33	5		T24	2
valid_sources[0x3c]	74816	1			T32	656		T33	2		T30	3
valid_sources[0x3d]	66785	1			T32	621		T33	9		T35	1
valid_sources[0x3e]	67013	1			T32	587		T33	3		T24	11
valid_sources[0x3f]	68021	1			T32	664		T33	4		T34	2
valid_sources[0x40]	63886	1			T32	601		T33	10		T23	1
valid_sources[0x41]	64038	1			T32	630		T33	6		T35	3
valid_sources[0x42]	75462	1			T32	601		T33	4		T36	42
valid_sources[0x43]	71408	1			T32	616		T33	8		T34	1
valid_sources[0x44]	198052	1			T32	625		T33	10		T24	8
valid_sources[0x45]	206960	1			T32	577		T33	11		T34	2
valid_sources[0x46]	67689	1			T32	610		T33	6		T34	1
valid_sources[0x47]	66309	1			T32	641		T33	8		T24	1
valid_sources[0x48]	80442	1			T32	617		T33	6		T34	1
valid_sources[0x49]	68084	1			T32	668		T33	3		T34	2
valid_sources[0x4a]	72835	1			T32	592		T34	2		T35	1
valid_sources[0x4b]	134155	1			T32	610		T33	3		T34	4
valid_sources[0x4c]	74073	1			T32	651		T33	4		T24	22
valid_sources[0x4d]	68321	1			T32	584		T33	5		T23	1
valid_sources[0x4e]	65929	1			T32	617		T33	5		T34	1
valid_sources[0x4f]	197889	1			T32	625		T33	4		T34	1
valid_sources[0x50]	68945	1			T32	635		T33	7		T34	1
valid_sources[0x51]	68147	1			T32	616		T33	9		T34	1
valid_sources[0x52]	65477	1			T32	618		T33	1		T34	2
valid_sources[0x53]	65366	1			T32	591		T33	2		T34	1
valid_sources[0x54]	64509	1			T32	625		T35	6		T36	12
valid_sources[0x55]	68440	1			T32	638		T33	8		T24	6
valid_sources[0x56]	71839	1			T32	609		T33	2		T34	2
valid_sources[0x57]	65356	1			T32	598		T33	12		T34	1
valid_sources[0x58]	72756	1			T32	654		T33	7		T34	1
valid_sources[0x59]	66598	1			T32	602		T33	2		T35	2
valid_sources[0x5a]	72616	1			T32	597		T33	7		T34	1
valid_sources[0x5b]	66810	1			T32	621		T33	12		T35	3
valid_sources[0x5c]	70092	1			T32	622		T33	13		T35	3
valid_sources[0x5d]	73662	1			T32	627		T33	5		T35	5
valid_sources[0x5e]	74564	1			T32	600		T33	13		T34	3
valid_sources[0x5f]	63488	1			T32	624		T33	11		T34	1
valid_sources[0x60]	123816	1			T32	680		T33	6		T36	23
valid_sources[0x61]	71070	1			T32	603		T33	6		T34	1
valid_sources[0x62]	68749	1			T32	633		T33	9		T24	19
valid_sources[0x63]	67903	1			T32	549		T33	8		T34	4
valid_sources[0x64]	70220	1			T32	584		T33	2		T34	1
valid_sources[0x65]	74689	1			T32	609		T33	3		T24	16
valid_sources[0x66]	71603	1			T32	641		T33	7		T35	1
valid_sources[0x67]	73341	1			T32	639		T33	3		T34	1
valid_sources[0x68]	68994	1			T32	574		T33	9		T36	8
valid_sources[0x69]	64271	1			T32	566		T33	8		T36	9
valid_sources[0x6a]	159930	1			T32	646		T33	3		T34	1
valid_sources[0x6b]	72420	1			T32	548		T33	9		T34	2
valid_sources[0x6c]	67148	1			T32	554		T33	19		T34	1
valid_sources[0x6d]	76303	1			T32	618		T33	6		T35	6
valid_sources[0x6e]	68054	1			T32	648		T33	3		T24	13
valid_sources[0x6f]	73732	1			T32	611		T33	1		T35	1
valid_sources[0x70]	73594	1			T32	599		T33	3		T24	2
valid_sources[0x71]	109561	1			T32	593		T33	4		T35	4
valid_sources[0x72]	67344	1			T32	620		T33	4		T34	1
valid_sources[0x73]	68147	1			T32	576		T33	7		T34	3
valid_sources[0x74]	69422	1			T32	591		T33	6		T34	2
valid_sources[0x75]	68079	1			T32	619		T33	5		T34	4
valid_sources[0x76]	67949	1			T32	684		T33	3		T24	15
valid_sources[0x77]	74203	1			T32	646		T33	18		T35	3
valid_sources[0x78]	71752	1			T32	610		T33	4		T35	1
valid_sources[0x79]	65535	1			T32	595		T33	5		T34	1
valid_sources[0x7a]	66333	1			T32	674		T33	5		T34	2
valid_sources[0x7b]	67290	1			T32	625		T33	3		T34	1
valid_sources[0x7c]	71495	1			T32	611		T33	8		T36	32
valid_sources[0x7d]	72263	1			T32	571		T33	9		T34	2
valid_sources[0x7e]	69517	1			T32	597		T33	5		T34	4
valid_sources[0x7f]	70887	1			T32	557		T24	17		T25	3
valid_sources[0x80]	74462	1			T32	651		T33	3		T36	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4400292

1

T32

35392

T33

553

T34

35

values[0x0]

all_enables

biggest_size

5632323

1

T32

44404

T33

184

T34

62

values[0x1]

all_enables

biggest_size

5637631

1

T32

43860

T33

158

T34

66