Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	156184324	0	0	0
ctrl_en_input_filter_rd_A	156184324	65352	0	0
intr_ctrl_en_falling_rd_A	156184324	66558	0	0
intr_ctrl_en_lvlhigh_rd_A	156184324	64854	0	0
intr_ctrl_en_lvllow_rd_A	156184324	66689	0	0
intr_ctrl_en_rising_rd_A	156184324	65652	0	0
intr_enable_rd_A	156184324	65506	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156184324	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156184324	65352	0	0
T1	245752	634	0	0
T2	0	5138	0	0
T3	0	2782	0	0
T4	0	8618	0	0
T5	0	107	0	0
T6	0	1009	0	0
T7	0	249	0	0
T8	0	14410	0	0
T9	0	332	0	0
T10	0	140	0	0
T11	17714	0	0	0
T12	3265	0	0	0
T13	39079	0	0	0
T14	6990	0	0	0
T15	6864	0	0	0
T16	2008	0	0	0
T17	2715	0	0	0
T18	10047	0	0	0
T19	3620	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156184324	66558	0	0
T1	245752	815	0	0
T2	0	5585	0	0
T3	0	2948	0	0
T4	0	8424	0	0
T5	0	141	0	0
T6	0	1232	0	0
T7	0	288	0	0
T8	0	14987	0	0
T9	0	455	0	0
T10	0	127	0	0
T11	17714	0	0	0
T12	3265	0	0	0
T13	39079	0	0	0
T14	6990	0	0	0
T15	6864	0	0	0
T16	2008	0	0	0
T17	2715	0	0	0
T18	10047	0	0	0
T19	3620	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156184324	64854	0	0
T1	0	693	0	0
T2	0	5184	0	0
T3	0	2830	0	0
T4	0	8307	0	0
T5	0	69	0	0
T6	0	1134	0	0
T7	0	359	0	0
T20	8044	3	0	0
T21	0	6	0	0
T22	0	1	0	0
T23	1279	0	0	0
T24	8713	0	0	0
T25	3376	0	0	0
T26	204907	0	0	0
T27	10236	0	0	0
T28	2925	0	0	0
T29	3549	0	0	0
T30	3437	0	0	0
T31	4857	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156184324	66689	0	0
T1	0	686	0	0
T2	0	5291	0	0
T3	0	2778	0	0
T4	0	8418	0	0
T5	0	146	0	0
T6	0	1044	0	0
T7	0	264	0	0
T8	0	15616	0	0
T9	0	283	0	0
T20	8044	6	0	0
T23	1279	0	0	0
T24	8713	0	0	0
T25	3376	0	0	0
T26	204907	0	0	0
T27	10236	0	0	0
T28	2925	0	0	0
T29	3549	0	0	0
T30	3437	0	0	0
T31	4857	0	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156184324	65652	0	0
T1	0	642	0	0
T2	0	5017	0	0
T3	0	2643	0	0
T4	0	8128	0	0
T5	0	171	0	0
T6	0	1193	0	0
T7	0	341	0	0
T8	0	14691	0	0
T20	8044	3	0	0
T22	0	6	0	0
T23	1279	0	0	0
T24	8713	0	0	0
T25	3376	0	0	0
T26	204907	0	0	0
T27	10236	0	0	0
T28	2925	0	0	0
T29	3549	0	0	0
T30	3437	0	0	0
T31	4857	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156184324	65506	0	0
T1	245752	777	0	0
T2	0	5227	0	0
T3	0	2727	0	0
T4	0	8210	0	0
T5	0	128	0	0
T6	0	1204	0	0
T7	0	405	0	0
T8	0	14769	0	0
T9	0	370	0	0
T10	0	130	0	0
T11	17714	0	0	0
T12	3265	0	0	0
T13	39079	0	0	0
T14	6990	0	0	0
T15	6864	0	0	0
T16	2008	0	0	0
T17	2715	0	0	0
T18	10047	0	0	0
T19	3620	0	0	0