Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1482706	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5240041

1

T29

376

T30

156

T31

1997

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3007452	1			T29	90		T30	191		T31	3050
values[0x0]	1850864	1			T29	172		T30	33		T31	219
values[0x1]	1864431	1			T29	159		T30	35		T31	219

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1177887	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5544860

1

T29

388

T30

177

T31

2298

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26416	1			T29	1		T31	19		T32	3
valid_sources[0x01]	21056	1			T30	2		T31	13		T14	1
valid_sources[0x02]	22331	1			T29	3		T31	8		T32	1
valid_sources[0x03]	28783	1			T29	2		T30	2		T31	13
valid_sources[0x04]	22794	1			T29	1		T30	1		T31	16
valid_sources[0x05]	22132	1			T29	4		T30	2		T31	13
valid_sources[0x06]	22430	1			T29	3		T31	10		T14	2
valid_sources[0x07]	30929	1			T29	2		T30	2		T31	9
valid_sources[0x08]	24971	1			T29	2		T30	2		T31	10
valid_sources[0x09]	21583	1			T29	3		T30	2		T31	12
valid_sources[0x0a]	20684	1			T29	1		T30	1		T31	10
valid_sources[0x0b]	23516	1			T29	3		T30	2		T31	23
valid_sources[0x0c]	21734	1			T29	1		T30	2		T31	17
valid_sources[0x0d]	23285	1			T29	1		T30	1		T31	4
valid_sources[0x0e]	23805	1			T29	2		T31	15		T32	1
valid_sources[0x0f]	22600	1			T29	3		T31	9		T32	2
valid_sources[0x10]	23249	1			T29	4		T30	2		T31	9
valid_sources[0x11]	20708	1			T29	1		T31	10		T14	1
valid_sources[0x12]	20326	1			T30	1		T31	17		T32	2
valid_sources[0x13]	24203	1			T29	3		T30	1		T31	14
valid_sources[0x14]	23044	1			T29	2		T30	3		T31	10
valid_sources[0x15]	68586	1			T30	1		T31	17		T32	1
valid_sources[0x16]	21816	1			T29	3		T30	2		T31	15
valid_sources[0x17]	25190	1			T29	5		T31	17		T16	605
valid_sources[0x18]	21166	1			T29	2		T31	13		T32	2
valid_sources[0x19]	21491	1			T31	17		T32	1		T14	1
valid_sources[0x1a]	21606	1			T29	1		T31	13		T32	1
valid_sources[0x1b]	25838	1			T29	1		T31	13		T14	1
valid_sources[0x1c]	23374	1			T30	1		T31	13		T32	1
valid_sources[0x1d]	21943	1			T29	2		T31	14		T15	1
valid_sources[0x1e]	23599	1			T29	3		T30	1		T31	12
valid_sources[0x1f]	23639	1			T29	2		T30	3		T31	10
valid_sources[0x20]	27275	1			T29	1		T31	16		T32	1
valid_sources[0x21]	26566	1			T30	5		T31	11		T32	2
valid_sources[0x22]	25449	1			T29	1		T31	16		T14	1
valid_sources[0x23]	21935	1			T29	1		T30	1		T31	17
valid_sources[0x24]	150439	1			T29	2		T31	6		T14	1
valid_sources[0x25]	25812	1			T29	2		T30	4		T31	16
valid_sources[0x26]	24176	1			T29	3		T31	14		T16	528
valid_sources[0x27]	21823	1			T29	3		T30	1		T31	9
valid_sources[0x28]	22826	1			T29	1		T30	2		T31	11
valid_sources[0x29]	23896	1			T29	8		T30	1		T31	12
valid_sources[0x2a]	24062	1			T29	1		T30	1		T31	13
valid_sources[0x2b]	25268	1			T29	4		T30	3		T31	18
valid_sources[0x2c]	21727	1			T30	1		T31	10		T14	2
valid_sources[0x2d]	21098	1			T29	1		T31	18		T16	535
valid_sources[0x2e]	21764	1			T29	2		T30	1		T31	15
valid_sources[0x2f]	29957	1			T29	1		T30	1		T31	12
valid_sources[0x30]	23753	1			T30	1		T31	14		T32	1
valid_sources[0x31]	27060	1			T29	1		T31	21		T14	2
valid_sources[0x32]	22595	1			T29	3		T31	11		T14	1
valid_sources[0x33]	22408	1			T29	2		T31	18		T16	575
valid_sources[0x34]	22437	1			T29	3		T30	3		T31	17
valid_sources[0x35]	22582	1			T29	2		T31	18		T15	2
valid_sources[0x36]	21872	1			T30	1		T31	20		T32	2
valid_sources[0x37]	22027	1			T31	7		T14	1		T16	699
valid_sources[0x38]	29063	1			T29	6		T30	1		T31	12
valid_sources[0x39]	23837	1			T29	6		T30	1		T31	19
valid_sources[0x3a]	24853	1			T31	18		T32	1		T15	11
valid_sources[0x3b]	25543	1			T31	7		T32	2		T14	1
valid_sources[0x3c]	22821	1			T29	2		T31	10		T14	1
valid_sources[0x3d]	22760	1			T29	2		T30	1		T31	11
valid_sources[0x3e]	23314	1			T29	2		T31	13		T14	2
valid_sources[0x3f]	98448	1			T29	1		T30	1		T31	18
valid_sources[0x40]	22039	1			T29	3		T30	1		T31	12
valid_sources[0x41]	21380	1			T29	2		T30	3		T31	12
valid_sources[0x42]	21722	1			T29	1		T30	1		T31	12
valid_sources[0x43]	21382	1			T29	2		T30	2		T31	8
valid_sources[0x44]	22632	1			T30	1		T31	16		T32	1
valid_sources[0x45]	21429	1			T29	2		T30	1		T31	19
valid_sources[0x46]	22203	1			T29	2		T30	1		T31	19
valid_sources[0x47]	24814	1			T29	1		T30	1		T31	19
valid_sources[0x48]	22796	1			T29	1		T31	9		T32	1
valid_sources[0x49]	21927	1			T30	1		T31	16		T32	1
valid_sources[0x4a]	20831	1			T29	1		T31	10		T14	1
valid_sources[0x4b]	20604	1			T29	1		T30	1		T31	9
valid_sources[0x4c]	21711	1			T29	1		T30	3		T31	8
valid_sources[0x4d]	23580	1			T29	2		T30	1		T31	13
valid_sources[0x4e]	22159	1			T29	3		T30	4		T31	17
valid_sources[0x4f]	27200	1			T29	3		T31	13		T14	1
valid_sources[0x50]	21264	1			T29	3		T31	19		T32	1
valid_sources[0x51]	25537	1			T29	1		T30	1		T31	12
valid_sources[0x52]	22985	1			T29	1		T31	23		T15	3
valid_sources[0x53]	27246	1			T29	1		T30	1		T31	21
valid_sources[0x54]	21523	1			T30	2		T31	8		T16	597
valid_sources[0x55]	23497	1			T29	1		T30	2		T31	11
valid_sources[0x56]	24545	1			T29	1		T30	2		T31	14
valid_sources[0x57]	20682	1			T29	2		T30	2		T31	16
valid_sources[0x58]	27393	1			T31	9		T14	1		T15	6
valid_sources[0x59]	27129	1			T29	2		T30	1		T31	8
valid_sources[0x5a]	23429	1			T29	1		T30	1		T31	17
valid_sources[0x5b]	21743	1			T29	4		T30	1		T31	15
valid_sources[0x5c]	22135	1			T29	3		T31	10		T32	2
valid_sources[0x5d]	22205	1			T29	2		T30	1		T31	16
valid_sources[0x5e]	21090	1			T29	3		T30	2		T31	16
valid_sources[0x5f]	26870	1			T29	2		T30	4		T31	5
valid_sources[0x60]	22812	1			T29	3		T30	1		T31	13
valid_sources[0x61]	22573	1			T29	3		T30	2		T31	12
valid_sources[0x62]	21787	1			T29	3		T30	1		T31	6
valid_sources[0x63]	23397	1			T29	1		T31	16		T14	1
valid_sources[0x64]	21254	1			T29	1		T30	1		T31	11
valid_sources[0x65]	22579	1			T29	2		T30	1		T31	15
valid_sources[0x66]	22054	1			T29	2		T30	5		T31	19
valid_sources[0x67]	21458	1			T29	1		T31	13		T14	3
valid_sources[0x68]	20427	1			T29	2		T30	1		T31	14
valid_sources[0x69]	22977	1			T29	2		T31	11		T32	1
valid_sources[0x6a]	21803	1			T29	3		T31	12		T32	2
valid_sources[0x6b]	25277	1			T29	4		T30	1		T31	16
valid_sources[0x6c]	24396	1			T29	2		T30	1		T31	12
valid_sources[0x6d]	21598	1			T30	1		T31	8		T32	1
valid_sources[0x6e]	23685	1			T31	19		T32	2		T14	1
valid_sources[0x6f]	21682	1			T29	4		T31	16		T32	1
valid_sources[0x70]	22010	1			T30	2		T31	14		T32	2
valid_sources[0x71]	24090	1			T29	2		T31	13		T16	572
valid_sources[0x72]	22309	1			T30	1		T31	18		T32	1
valid_sources[0x73]	21536	1			T29	5		T30	2		T31	5
valid_sources[0x74]	21749	1			T29	3		T30	2		T31	9
valid_sources[0x75]	21231	1			T29	1		T31	13		T16	734
valid_sources[0x76]	178555	1			T29	2		T30	1		T31	13
valid_sources[0x77]	22756	1			T29	1		T30	3		T31	20
valid_sources[0x78]	24509	1			T29	2		T31	12		T32	3
valid_sources[0x79]	23678	1			T30	1		T31	15		T15	1
valid_sources[0x7a]	23728	1			T29	4		T30	1		T31	17
valid_sources[0x7b]	21092	1			T29	2		T30	2		T31	13
valid_sources[0x7c]	24012	1			T31	11		T16	580		T17	207
valid_sources[0x7d]	24168	1			T29	2		T31	11		T32	2
valid_sources[0x7e]	22136	1			T29	3		T30	1		T31	14
valid_sources[0x7f]	22541	1			T30	1		T31	14		T14	1
valid_sources[0x80]	25304	1			T29	2		T31	8		T16	615

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1541592

1

T29

45

T30

88

T31

1559

values[0x0]

all_enables

biggest_size

1848915

1

T29

172

T30

33

T31

219

values[0x1]

all_enables

biggest_size

1849534

1

T29

159

T30

35

T31

219