Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	56779612	0	0	0
ctrl_en_input_filter_rd_A	56779612	92562	0	0
intr_ctrl_en_falling_rd_A	56779612	92546	0	0
intr_ctrl_en_lvlhigh_rd_A	56779612	93041	0	0
intr_ctrl_en_lvllow_rd_A	56779612	92590	0	0
intr_ctrl_en_rising_rd_A	56779612	92544	0	0
intr_enable_rd_A	56779612	91399	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56779612	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56779612	92562	0	0
T1	4698	9	0	0
T2	0	932	0	0
T3	0	3057	0	0
T4	0	128	0	0
T5	0	4555	0	0
T6	0	18	0	0
T7	0	3546	0	0
T8	0	5559	0	0
T9	0	2420	0	0
T10	0	4931	0	0
T11	3253	0	0	0
T12	5028	0	0	0
T13	1523	0	0	0
T14	2420	0	0	0
T15	2643	0	0	0
T16	708811	0	0	0
T17	219309	0	0	0
T18	22450	0	0	0
T19	2617	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56779612	92546	0	0
T2	600019	850	0	0
T3	872841	3114	0	0
T4	0	192	0	0
T5	0	4800	0	0
T6	0	64	0	0
T7	0	3314	0	0
T8	0	5676	0	0
T9	0	2411	0	0
T10	0	5058	0	0
T20	0	70	0	0
T21	3895	0	0	0
T22	3348	0	0	0
T23	7666	0	0	0
T24	4403	0	0	0
T25	4445	0	0	0
T26	41901	0	0	0
T27	1363	0	0	0
T28	5017	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56779612	93041	0	0
T2	600019	869	0	0
T3	872841	2923	0	0
T4	0	133	0	0
T5	0	4903	0	0
T6	0	63	0	0
T7	0	3504	0	0
T8	0	5195	0	0
T9	0	2527	0	0
T10	0	4667	0	0
T20	0	81	0	0
T21	3895	0	0	0
T22	3348	0	0	0
T23	7666	0	0	0
T24	4403	0	0	0
T25	4445	0	0	0
T26	41901	0	0	0
T27	1363	0	0	0
T28	5017	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56779612	92590	0	0
T2	600019	970	0	0
T3	872841	3126	0	0
T4	0	130	0	0
T5	0	4655	0	0
T6	0	25	0	0
T7	0	3662	0	0
T8	0	5423	0	0
T9	0	2516	0	0
T10	0	4946	0	0
T20	0	70	0	0
T21	3895	0	0	0
T22	3348	0	0	0
T23	7666	0	0	0
T24	4403	0	0	0
T25	4445	0	0	0
T26	41901	0	0	0
T27	1363	0	0	0
T28	5017	0	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56779612	92544	0	0
T2	600019	942	0	0
T3	872841	3197	0	0
T4	0	123	0	0
T5	0	5040	0	0
T6	0	48	0	0
T7	0	3870	0	0
T8	0	5498	0	0
T9	0	2092	0	0
T10	0	4792	0	0
T20	0	62	0	0
T21	3895	0	0	0
T22	3348	0	0	0
T23	7666	0	0	0
T24	4403	0	0	0
T25	4445	0	0	0
T26	41901	0	0	0
T27	1363	0	0	0
T28	5017	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56779612	91399	0	0
T2	600019	980	0	0
T3	872841	3201	0	0
T4	0	121	0	0
T5	0	4717	0	0
T6	0	34	0	0
T7	0	3595	0	0
T8	0	5130	0	0
T9	0	2490	0	0
T10	0	4894	0	0
T20	0	54	0	0
T21	3895	0	0	0
T22	3348	0	0	0
T23	7666	0	0	0
T24	4403	0	0	0
T25	4445	0	0	0
T26	41901	0	0	0
T27	1363	0	0	0
T28	5017	0	0	0