Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1282096	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4444257

1

T34

10

T35

269

T36

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2590870	1			T34	1		T35	297		T36	1
values[0x0]	1563305	1			T34	14		T35	52		T36	7
values[0x1]	1572178	1			T34	9		T35	66		T36	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1021364	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4704989

1

T34

10

T35

295

T36

5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18254	1			T35	2		T44	512		T45	2
valid_sources[0x01]	17948	1			T44	481		T45	1		T61	9
valid_sources[0x02]	71584	1			T35	6		T38	1		T42	1
valid_sources[0x03]	48551	1			T35	3		T38	2		T44	528
valid_sources[0x04]	18919	1			T38	6		T44	570		T45	3
valid_sources[0x05]	21764	1			T35	7		T38	5		T42	1
valid_sources[0x06]	19026	1			T35	3		T37	1		T38	2
valid_sources[0x07]	17573	1			T38	1		T44	539		T60	2
valid_sources[0x08]	20071	1			T35	1		T38	3		T41	1
valid_sources[0x09]	19697	1			T35	1		T38	5		T44	506
valid_sources[0x0a]	17366	1			T43	4		T44	488		T45	6
valid_sources[0x0b]	17432	1			T35	1		T38	4		T41	2
valid_sources[0x0c]	17745	1			T35	1		T42	2		T44	499
valid_sources[0x0d]	18005	1			T35	3		T38	1		T43	9
valid_sources[0x0e]	17963	1			T35	6		T37	5		T38	1
valid_sources[0x0f]	17996	1			T41	2		T42	1		T44	502
valid_sources[0x10]	17989	1			T35	4		T38	7		T44	526
valid_sources[0x11]	18688	1			T35	2		T44	535		T45	5
valid_sources[0x12]	20702	1			T35	3		T43	7		T44	544
valid_sources[0x13]	18325	1			T35	2		T38	1		T44	512
valid_sources[0x14]	17885	1			T35	3		T44	506		T60	1
valid_sources[0x15]	17349	1			T35	3		T44	482		T61	13
valid_sources[0x16]	56350	1			T35	2		T44	547		T60	1
valid_sources[0x17]	18231	1			T35	1		T42	1		T44	518
valid_sources[0x18]	17747	1			T38	3		T44	566		T60	1
valid_sources[0x19]	20874	1			T35	1		T38	2		T41	3
valid_sources[0x1a]	17597	1			T35	1		T44	537		T45	3
valid_sources[0x1b]	17826	1			T35	1		T44	498		T45	4
valid_sources[0x1c]	20437	1			T36	1		T42	2		T44	516
valid_sources[0x1d]	19129	1			T35	1		T44	557		T61	2
valid_sources[0x1e]	18755	1			T35	5		T38	10		T42	1
valid_sources[0x1f]	20025	1			T35	5		T37	7		T42	1
valid_sources[0x20]	17342	1			T35	1		T37	4		T44	499
valid_sources[0x21]	19573	1			T37	14		T42	1		T44	545
valid_sources[0x22]	18154	1			T35	3		T38	8		T44	535
valid_sources[0x23]	18981	1			T38	2		T41	1		T42	3
valid_sources[0x24]	18054	1			T35	3		T44	532		T60	1
valid_sources[0x25]	18584	1			T37	1		T38	7		T41	10
valid_sources[0x26]	18124	1			T35	6		T44	558		T60	2
valid_sources[0x27]	17590	1			T35	2		T38	1		T44	540
valid_sources[0x28]	17704	1			T42	1		T44	443		T60	1
valid_sources[0x29]	19778	1			T35	1		T38	3		T44	530
valid_sources[0x2a]	17527	1			T35	1		T37	3		T44	533
valid_sources[0x2b]	18292	1			T35	2		T41	3		T43	6
valid_sources[0x2c]	18011	1			T42	1		T44	535		T60	1
valid_sources[0x2d]	20649	1			T35	2		T42	1		T43	1
valid_sources[0x2e]	23362	1			T35	6		T38	9		T44	464
valid_sources[0x2f]	19164	1			T35	1		T42	1		T44	566
valid_sources[0x30]	18204	1			T35	3		T37	5		T44	547
valid_sources[0x31]	18157	1			T35	4		T44	526		T61	7
valid_sources[0x32]	20440	1			T35	1		T38	1		T41	3
valid_sources[0x33]	19681	1			T35	1		T37	5		T38	1
valid_sources[0x34]	18264	1			T38	2		T42	1		T44	537
valid_sources[0x35]	17825	1			T35	1		T38	3		T41	1
valid_sources[0x36]	18285	1			T35	3		T37	3		T44	531
valid_sources[0x37]	17887	1			T38	2		T44	504		T60	2
valid_sources[0x38]	20116	1			T35	3		T37	3		T38	11
valid_sources[0x39]	17360	1			T35	1		T37	2		T42	1
valid_sources[0x3a]	19511	1			T35	1		T44	494		T45	2
valid_sources[0x3b]	17847	1			T35	1		T36	1		T43	5
valid_sources[0x3c]	17860	1			T35	1		T37	5		T38	2
valid_sources[0x3d]	18062	1			T37	10		T44	535		T61	6
valid_sources[0x3e]	17904	1			T41	1		T44	496		T45	2
valid_sources[0x3f]	18140	1			T35	1		T38	4		T44	540
valid_sources[0x40]	18063	1			T35	1		T37	2		T44	594
valid_sources[0x41]	19573	1			T35	2		T37	9		T38	1
valid_sources[0x42]	19526	1			T37	2		T38	1		T44	500
valid_sources[0x43]	17950	1			T35	1		T41	3		T44	553
valid_sources[0x44]	17789	1			T35	5		T38	5		T44	509
valid_sources[0x45]	18606	1			T44	506		T45	2		T60	1
valid_sources[0x46]	17935	1			T35	5		T37	3		T38	9
valid_sources[0x47]	18244	1			T35	1		T37	3		T38	6
valid_sources[0x48]	21353	1			T35	1		T36	1		T39	370
valid_sources[0x49]	17469	1			T35	3		T44	560		T61	5
valid_sources[0x4a]	18364	1			T35	1		T38	3		T44	519
valid_sources[0x4b]	18520	1			T35	3		T38	2		T42	1
valid_sources[0x4c]	70911	1			T44	512		T45	2		T60	1
valid_sources[0x4d]	18273	1			T35	2		T42	2		T44	549
valid_sources[0x4e]	17985	1			T35	6		T38	1		T44	491
valid_sources[0x4f]	18341	1			T35	4		T41	2		T44	508
valid_sources[0x50]	19359	1			T44	531		T60	1		T61	8
valid_sources[0x51]	21000	1			T35	2		T42	2		T44	492
valid_sources[0x52]	18673	1			T35	5		T38	2		T44	496
valid_sources[0x53]	18842	1			T35	2		T41	2		T44	516
valid_sources[0x54]	20585	1			T41	3		T44	476		T45	3
valid_sources[0x55]	17546	1			T35	2		T37	3		T38	1
valid_sources[0x56]	17257	1			T35	4		T37	1		T38	2
valid_sources[0x57]	17581	1			T44	537		T60	1		T61	6
valid_sources[0x58]	17955	1			T35	2		T42	1		T44	592
valid_sources[0x59]	65221	1			T35	4		T44	524		T45	1
valid_sources[0x5a]	19261	1			T44	603		T45	2		T60	1
valid_sources[0x5b]	17931	1			T35	3		T44	498		T61	4
valid_sources[0x5c]	18199	1			T35	1		T37	3		T44	533
valid_sources[0x5d]	19194	1			T35	2		T44	576		T45	1
valid_sources[0x5e]	18492	1			T35	2		T44	528		T45	2
valid_sources[0x5f]	18039	1			T37	6		T44	529		T45	3
valid_sources[0x60]	17799	1			T35	2		T43	4		T44	520
valid_sources[0x61]	17998	1			T35	1		T42	1		T44	542
valid_sources[0x62]	17578	1			T37	11		T38	4		T44	554
valid_sources[0x63]	20646	1			T35	1		T41	3		T44	477
valid_sources[0x64]	18633	1			T38	5		T41	4		T44	551
valid_sources[0x65]	18643	1			T35	2		T41	3		T43	2
valid_sources[0x66]	20786	1			T35	1		T36	1		T38	3
valid_sources[0x67]	17176	1			T35	4		T38	1		T44	502
valid_sources[0x68]	18049	1			T35	2		T42	1		T44	576
valid_sources[0x69]	19270	1			T35	1		T42	1		T43	2
valid_sources[0x6a]	18272	1			T37	7		T38	2		T42	2
valid_sources[0x6b]	17654	1			T35	3		T37	2		T44	559
valid_sources[0x6c]	20679	1			T35	3		T42	1		T44	556
valid_sources[0x6d]	18030	1			T35	1		T38	2		T42	1
valid_sources[0x6e]	19425	1			T38	1		T44	509		T45	1
valid_sources[0x6f]	18372	1			T37	3		T38	3		T44	496
valid_sources[0x70]	20859	1			T35	3		T37	4		T44	537
valid_sources[0x71]	17714	1			T35	2		T38	2		T44	489
valid_sources[0x72]	19025	1			T38	7		T44	558		T115	583
valid_sources[0x73]	18516	1			T35	3		T44	525		T60	2
valid_sources[0x74]	17717	1			T37	2		T42	1		T44	535
valid_sources[0x75]	19178	1			T35	1		T42	1		T44	518
valid_sources[0x76]	18935	1			T35	2		T37	5		T38	1
valid_sources[0x77]	18007	1			T41	1		T44	530		T45	1
valid_sources[0x78]	20471	1			T35	2		T44	519		T45	3
valid_sources[0x79]	180533	1			T35	2		T44	531		T45	3
valid_sources[0x7a]	17616	1			T44	536		T45	5		T60	1
valid_sources[0x7b]	17612	1			T37	2		T38	12		T44	478
valid_sources[0x7c]	84051	1			T35	3		T42	1		T44	553
valid_sources[0x7d]	75466	1			T35	1		T43	2		T44	547
valid_sources[0x7e]	18829	1			T35	7		T37	2		T44	551
valid_sources[0x7f]	18602	1			T38	1		T42	1		T44	515
valid_sources[0x80]	18215	1			T44	598		T45	1		T60	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1318644

1

T34

1

T35

151

T36

1

values[0x0]

all_enables

biggest_size

1562036

1

T34

4

T35

52

T36

2

values[0x1]

all_enables

biggest_size

1563577

1

T34

5

T35

66

T36

1