Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	48522505	0	0	0
ctrl_en_input_filter_rd_A	48522505	45321	0	0
intr_ctrl_en_falling_rd_A	48522505	44558	0	0
intr_ctrl_en_lvlhigh_rd_A	48522505	44725	0	0
intr_ctrl_en_lvllow_rd_A	48522505	44812	0	0
intr_ctrl_en_rising_rd_A	48522505	45843	0	0
intr_enable_rd_A	48522505	45058	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48522505	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48522505	45321	0	0
T1	29342	188	0	0
T2	0	151	0	0
T3	0	136	0	0
T4	0	537	0	0
T5	0	1646	0	0
T6	0	3992	0	0
T7	0	2902	0	0
T8	0	279	0	0
T9	0	402	0	0
T10	0	281	0	0
T11	10654	0	0	0
T12	2217	0	0	0
T13	26629	0	0	0
T14	4832	0	0	0
T15	4276	0	0	0
T16	7480	0	0	0
T17	4565	0	0	0
T18	278551	0	0	0
T19	3788	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48522505	44558	0	0
T1	0	90	0	0
T2	0	145	0	0
T3	0	123	0	0
T4	0	463	0	0
T5	0	1566	0	0
T6	0	3831	0	0
T7	0	3059	0	0
T8	0	224	0	0
T9	0	368	0	0
T20	6397	9	0	0
T21	3399	0	0	0
T22	43322	0	0	0
T23	1393	0	0	0
T24	881	0	0	0
T25	15908	0	0	0
T26	3899	0	0	0
T27	85376	0	0	0
T28	7415	0	0	0
T29	3321	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48522505	44725	0	0
T1	0	123	0	0
T2	0	236	0	0
T3	0	84	0	0
T4	0	419	0	0
T5	0	1797	0	0
T6	0	3897	0	0
T7	0	2785	0	0
T8	0	207	0	0
T20	6397	3	0	0
T21	3399	0	0	0
T22	43322	0	0	0
T23	1393	0	0	0
T24	881	0	0	0
T25	15908	0	0	0
T26	3899	0	0	0
T27	85376	0	0	0
T28	7415	0	0	0
T29	3321	0	0	0
T30	0	7	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48522505	44812	0	0
T1	0	153	0	0
T2	0	205	0	0
T3	0	95	0	0
T4	0	525	0	0
T5	0	1698	0	0
T6	0	3906	0	0
T7	0	2799	0	0
T8	0	205	0	0
T9	0	428	0	0
T20	6397	1	0	0
T21	3399	0	0	0
T22	43322	0	0	0
T23	1393	0	0	0
T24	881	0	0	0
T25	15908	0	0	0
T26	3899	0	0	0
T27	85376	0	0	0
T28	7415	0	0	0
T29	3321	0	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48522505	45843	0	0
T1	0	166	0	0
T2	0	210	0	0
T3	0	131	0	0
T4	0	429	0	0
T5	0	1635	0	0
T6	0	4001	0	0
T7	0	2763	0	0
T8	0	252	0	0
T20	6397	1	0	0
T21	3399	0	0	0
T22	43322	0	0	0
T23	1393	0	0	0
T24	881	0	0	0
T25	15908	0	0	0
T26	3899	0	0	0
T27	85376	0	0	0
T28	7415	0	0	0
T29	3321	0	0	0
T31	0	5	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48522505	45058	0	0
T1	29342	123	0	0
T2	0	192	0	0
T3	0	97	0	0
T4	0	460	0	0
T5	0	1698	0	0
T6	0	3976	0	0
T7	0	2882	0	0
T11	10654	0	0	0
T12	2217	0	0	0
T13	26629	0	0	0
T14	4832	0	0	0
T15	4276	0	0	0
T16	7480	0	0	0
T17	4565	0	0	0
T18	278551	0	0	0
T19	3788	0	0	0
T31	0	7	0	0
T32	0	1	0	0
T33	0	2	0	0