Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1302349	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4578782

1

T21

374

T22

1218

T23

315

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2643581	1			T21	79		T22	1512		T23	158
values[0x0]	1613015	1			T21	174		T22	227		T23	112
values[0x1]	1624535	1			T21	156		T22	272		T23	116

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1035894	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4845237

1

T21

378

T22

1371

T23

329

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	21916	1			T22	2		T26	5		T29	1
valid_sources[0x01]	105556	1			T21	2		T22	5		T23	1
valid_sources[0x02]	21572	1			T21	24		T22	10		T23	5
valid_sources[0x03]	20010	1			T22	11		T23	2		T26	6
valid_sources[0x04]	20293	1			T22	3		T23	4		T26	4
valid_sources[0x05]	17773	1			T21	8		T22	2		T25	6
valid_sources[0x06]	17947	1			T22	10		T26	12		T28	1
valid_sources[0x07]	19749	1			T21	3		T22	2		T23	1
valid_sources[0x08]	17674	1			T22	13		T23	3		T26	10
valid_sources[0x09]	16757	1			T21	5		T22	4		T23	4
valid_sources[0x0a]	19880	1			T21	2		T22	5		T23	2
valid_sources[0x0b]	16560	1			T21	3		T22	9		T23	1
valid_sources[0x0c]	18795	1			T22	4		T23	4		T25	3
valid_sources[0x0d]	16259	1			T21	3		T22	4		T23	2
valid_sources[0x0e]	18472	1			T22	4		T23	3		T26	4
valid_sources[0x0f]	18053	1			T22	3		T26	4		T99	1
valid_sources[0x10]	16369	1			T21	4		T22	8		T23	4
valid_sources[0x11]	19533	1			T22	19		T23	2		T26	11
valid_sources[0x12]	21036	1			T22	9		T23	5		T26	2
valid_sources[0x13]	16784	1			T22	3		T25	4		T26	3
valid_sources[0x14]	16543	1			T22	5		T23	4		T26	3
valid_sources[0x15]	18261	1			T22	5		T23	1		T26	9
valid_sources[0x16]	18382	1			T21	10		T22	11		T23	4
valid_sources[0x17]	16092	1			T22	7		T23	4		T26	9
valid_sources[0x18]	16695	1			T22	6		T23	2		T25	2
valid_sources[0x19]	17588	1			T22	12		T23	8		T26	8
valid_sources[0x1a]	18630	1			T22	6		T26	9		T28	1
valid_sources[0x1b]	23585	1			T22	7		T23	2		T26	10
valid_sources[0x1c]	17858	1			T22	7		T23	4		T26	9
valid_sources[0x1d]	17211	1			T21	17		T22	10		T26	4
valid_sources[0x1e]	16618	1			T23	2		T25	1		T26	11
valid_sources[0x1f]	16611	1			T22	7		T23	3		T26	6
valid_sources[0x20]	21131	1			T21	1		T22	9		T23	1
valid_sources[0x21]	64999	1			T22	17		T23	3		T25	2
valid_sources[0x22]	20859	1			T22	3		T23	2		T26	6
valid_sources[0x23]	17593	1			T22	12		T23	1		T26	13
valid_sources[0x24]	16465	1			T22	20		T23	3		T26	11
valid_sources[0x25]	16487	1			T21	9		T22	8		T26	1
valid_sources[0x26]	23244	1			T22	7		T23	1		T26	10
valid_sources[0x27]	18001	1			T22	11		T26	8		T29	3
valid_sources[0x28]	19458	1			T22	3		T23	1		T26	10
valid_sources[0x29]	16816	1			T22	9		T23	1		T25	3
valid_sources[0x2a]	16064	1			T22	9		T23	3		T25	4
valid_sources[0x2b]	17022	1			T22	10		T25	1		T26	4
valid_sources[0x2c]	17721	1			T21	2		T22	6		T23	1
valid_sources[0x2d]	16865	1			T22	14		T23	3		T26	7
valid_sources[0x2e]	16148	1			T22	5		T26	7		T28	1
valid_sources[0x2f]	20628	1			T22	11		T23	2		T26	8
valid_sources[0x30]	16659	1			T22	5		T23	3		T25	8
valid_sources[0x31]	23775	1			T22	7		T23	1		T26	7
valid_sources[0x32]	19565	1			T21	52		T22	7		T26	14
valid_sources[0x33]	19254	1			T22	1		T26	2		T28	1
valid_sources[0x34]	20570	1			T22	5		T23	1		T26	8
valid_sources[0x35]	17278	1			T22	9		T23	5		T26	7
valid_sources[0x36]	53758	1			T22	4		T26	14		T28	1
valid_sources[0x37]	18010	1			T22	3		T23	1		T26	12
valid_sources[0x38]	20927	1			T22	8		T23	2		T26	11
valid_sources[0x39]	17048	1			T22	6		T26	7		T28	4
valid_sources[0x3a]	18495	1			T22	9		T26	4		T29	2
valid_sources[0x3b]	18295	1			T22	8		T26	12		T29	2
valid_sources[0x3c]	73244	1			T22	9		T23	5		T26	4
valid_sources[0x3d]	19465	1			T22	12		T23	6		T26	11
valid_sources[0x3e]	16730	1			T21	2		T22	12		T26	12
valid_sources[0x3f]	21846	1			T22	6		T23	3		T26	11
valid_sources[0x40]	16399	1			T22	8		T23	5		T25	2
valid_sources[0x41]	16964	1			T22	6		T23	2		T26	6
valid_sources[0x42]	16767	1			T22	6		T23	1		T25	2
valid_sources[0x43]	19385	1			T22	13		T23	1		T26	10
valid_sources[0x44]	21457	1			T22	11		T26	6		T29	2
valid_sources[0x45]	18655	1			T22	15		T26	6		T28	3
valid_sources[0x46]	16739	1			T22	12		T25	1		T26	6
valid_sources[0x47]	18976	1			T22	8		T23	2		T26	6
valid_sources[0x48]	17888	1			T22	12		T26	11		T30	1
valid_sources[0x49]	33999	1			T21	11		T22	8		T26	12
valid_sources[0x4a]	24473	1			T22	7		T23	1		T25	3
valid_sources[0x4b]	16353	1			T22	7		T23	2		T25	2
valid_sources[0x4c]	19956	1			T21	19		T22	14		T23	1
valid_sources[0x4d]	19723	1			T22	10		T23	4		T26	11
valid_sources[0x4e]	17682	1			T22	8		T23	4		T25	4
valid_sources[0x4f]	18649	1			T21	2		T22	8		T23	1
valid_sources[0x50]	16093	1			T22	1		T23	2		T25	1
valid_sources[0x51]	17978	1			T21	3		T22	2		T23	2
valid_sources[0x52]	17636	1			T22	3		T26	14		T28	1
valid_sources[0x53]	137806	1			T22	4		T25	3		T26	9
valid_sources[0x54]	22226	1			T22	14		T26	11		T99	1
valid_sources[0x55]	21264	1			T21	1		T22	14		T23	3
valid_sources[0x56]	17448	1			T22	5		T23	2		T25	4
valid_sources[0x57]	20777	1			T21	4		T22	1		T23	2
valid_sources[0x58]	18622	1			T22	2		T25	1		T26	4
valid_sources[0x59]	19919	1			T22	1		T23	1		T26	6
valid_sources[0x5a]	17830	1			T22	21		T23	1		T26	7
valid_sources[0x5b]	17615	1			T22	4		T26	12		T29	1
valid_sources[0x5c]	20817	1			T22	14		T26	4		T29	1
valid_sources[0x5d]	21470	1			T21	7		T22	9		T26	13
valid_sources[0x5e]	19013	1			T22	7		T23	1		T26	5
valid_sources[0x5f]	23161	1			T22	12		T23	3		T25	4
valid_sources[0x60]	19298	1			T22	3		T26	14		T30	4
valid_sources[0x61]	16890	1			T21	1		T22	8		T26	9
valid_sources[0x62]	16713	1			T23	2		T26	7		T28	2
valid_sources[0x63]	17542	1			T22	16		T23	1		T26	8
valid_sources[0x64]	18218	1			T22	4		T23	2		T26	14
valid_sources[0x65]	16363	1			T21	13		T22	4		T23	2
valid_sources[0x66]	17838	1			T21	15		T22	18		T25	4
valid_sources[0x67]	19376	1			T21	9		T22	11		T23	4
valid_sources[0x68]	25601	1			T22	18		T26	16		T28	1
valid_sources[0x69]	22282	1			T22	9		T25	2		T26	9
valid_sources[0x6a]	19785	1			T22	11		T23	1		T26	5
valid_sources[0x6b]	18113	1			T22	7		T26	9		T27	24
valid_sources[0x6c]	146602	1			T22	9		T23	1		T26	9
valid_sources[0x6d]	19883	1			T22	3		T23	6		T24	10
valid_sources[0x6e]	18945	1			T21	1		T22	7		T26	8
valid_sources[0x6f]	17866	1			T21	5		T22	15		T26	6
valid_sources[0x70]	20321	1			T22	10		T23	1		T26	3
valid_sources[0x71]	18212	1			T22	7		T23	1		T26	10
valid_sources[0x72]	103624	1			T22	16		T23	2		T26	10
valid_sources[0x73]	18059	1			T21	6		T22	11		T25	8
valid_sources[0x74]	17993	1			T22	3		T23	3		T26	12
valid_sources[0x75]	17121	1			T22	5		T23	1		T26	8
valid_sources[0x76]	18230	1			T22	1		T26	5		T29	1
valid_sources[0x77]	16559	1			T22	4		T23	1		T25	2
valid_sources[0x78]	17801	1			T22	4		T23	2		T26	11
valid_sources[0x79]	16667	1			T22	1		T26	7		T29	1
valid_sources[0x7a]	20113	1			T22	4		T23	1		T26	7
valid_sources[0x7b]	17427	1			T22	7		T23	3		T26	7
valid_sources[0x7c]	16869	1			T22	2		T26	11		T30	2
valid_sources[0x7d]	17735	1			T21	6		T22	5		T23	6
valid_sources[0x7e]	16853	1			T22	11		T26	6		T28	1
valid_sources[0x7f]	22691	1			T22	14		T23	1		T25	1
valid_sources[0x80]	17860	1			T22	6		T23	1		T26	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1354385

1

T21

44

T22

719

T23

87

values[0x0]

all_enables

biggest_size

1611444

1

T21

174

T22

227

T23

112

values[0x1]

all_enables

biggest_size

1612953

1

T21

156

T22

272

T23

116