Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	47933228	0	0	0
ctrl_en_input_filter_rd_A	47933228	47817	0	0
intr_ctrl_en_falling_rd_A	47933228	47942	0	0
intr_ctrl_en_lvlhigh_rd_A	47933228	47418	0	0
intr_ctrl_en_lvllow_rd_A	47933228	48444	0	0
intr_ctrl_en_rising_rd_A	47933228	46777	0	0
intr_enable_rd_A	47933228	48197	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47933228	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47933228	47817	0	0
T1	512867	2403	0	0
T2	39826	193	0	0
T3	36640	307	0	0
T4	0	62	0	0
T5	0	57	0	0
T6	0	34	0	0
T7	0	3082	0	0
T8	0	5044	0	0
T9	0	1	0	0
T10	0	5	0	0
T11	1850	0	0	0
T12	17097	0	0	0
T13	2235	0	0	0
T14	2649	0	0	0
T15	6925	0	0	0
T16	2886	0	0	0
T17	4105	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47933228	47942	0	0
T1	512867	2392	0	0
T2	39826	204	0	0
T3	36640	288	0	0
T4	0	46	0	0
T5	0	45	0	0
T6	0	44	0	0
T7	0	2972	0	0
T8	0	5219	0	0
T11	1850	0	0	0
T12	17097	0	0	0
T13	2235	0	0	0
T14	2649	0	0	0
T15	6925	0	0	0
T16	2886	0	0	0
T17	4105	0	0	0
T18	0	2	0	0
T19	0	174	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47933228	47418	0	0
T1	512867	2210	0	0
T2	39826	85	0	0
T3	36640	267	0	0
T4	0	54	0	0
T5	0	75	0	0
T6	0	23	0	0
T7	0	3095	0	0
T8	0	5456	0	0
T11	1850	0	0	0
T12	17097	0	0	0
T13	2235	0	0	0
T14	2649	0	0	0
T15	6925	0	0	0
T16	2886	0	0	0
T17	4105	0	0	0
T18	0	7	0	0
T19	0	149	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47933228	48444	0	0
T1	512867	2315	0	0
T2	39826	202	0	0
T3	36640	273	0	0
T4	0	76	0	0
T5	0	39	0	0
T6	0	80	0	0
T7	0	3186	0	0
T8	0	5346	0	0
T9	0	1	0	0
T11	1850	0	0	0
T12	17097	0	0	0
T13	2235	0	0	0
T14	2649	0	0	0
T15	6925	0	0	0
T16	2886	0	0	0
T17	4105	0	0	0
T18	0	10	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47933228	46777	0	0
T1	512867	2477	0	0
T2	39826	179	0	0
T3	36640	332	0	0
T4	0	68	0	0
T5	0	44	0	0
T6	0	62	0	0
T7	0	2970	0	0
T8	0	5000	0	0
T11	1850	0	0	0
T12	17097	0	0	0
T13	2235	0	0	0
T14	2649	0	0	0
T15	6925	0	0	0
T16	2886	0	0	0
T17	4105	0	0	0
T19	0	130	0	0
T20	0	119	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47933228	48197	0	0
T1	512867	2019	0	0
T2	39826	172	0	0
T3	36640	342	0	0
T4	0	63	0	0
T5	0	44	0	0
T6	0	52	0	0
T7	0	3191	0	0
T8	0	4966	0	0
T11	1850	0	0	0
T12	17097	0	0	0
T13	2235	0	0	0
T14	2649	0	0	0
T15	6925	0	0	0
T16	2886	0	0	0
T17	4105	0	0	0
T18	0	5	0	0
T19	0	219	0	0