Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1253094	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4486589

1

T19

2880

T20

7

T21

164

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2555726	1			T19	1334		T20	1		T21	37
values[0x0]	1584016	1			T19	1106		T20	8		T21	75
values[0x1]	1599941	1			T19	1121		T20	11		T21	70

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	995582	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4744101

1

T19

3030

T20

8

T21

168

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18837	1			T19	9		T21	1		T25	3
valid_sources[0x01]	18698	1			T19	11		T21	2		T38	1
valid_sources[0x02]	18969	1			T19	35		T25	1		T31	9
valid_sources[0x03]	19096	1			T19	16		T38	1		T31	3
valid_sources[0x04]	26237	1			T19	7		T31	1		T39	5
valid_sources[0x05]	18107	1			T19	3		T31	7		T39	10
valid_sources[0x06]	23969	1			T19	16		T21	3		T25	1
valid_sources[0x07]	20944	1			T21	3		T25	1		T31	7
valid_sources[0x08]	18398	1			T19	21		T21	4		T25	2
valid_sources[0x09]	18515	1			T19	33		T38	1		T31	4
valid_sources[0x0a]	19295	1			T19	7		T25	1		T38	1
valid_sources[0x0b]	20225	1			T19	1		T21	2		T31	1
valid_sources[0x0c]	20360	1			T19	5		T25	1		T31	7
valid_sources[0x0d]	21190	1			T19	28		T25	3		T31	7
valid_sources[0x0e]	22365	1			T19	21		T25	1		T31	7
valid_sources[0x0f]	17722	1			T19	38		T22	3		T31	6
valid_sources[0x10]	21244	1			T19	3		T21	1		T22	1
valid_sources[0x11]	21828	1			T19	18		T31	4		T39	7
valid_sources[0x12]	19556	1			T19	22		T25	1		T31	5
valid_sources[0x13]	24647	1			T19	13		T21	1		T25	1
valid_sources[0x14]	20885	1			T19	38		T21	2		T25	3
valid_sources[0x15]	17756	1			T19	29		T31	5		T39	9
valid_sources[0x16]	18487	1			T19	1		T21	1		T31	8
valid_sources[0x17]	19734	1			T19	2		T25	1		T28	480
valid_sources[0x18]	23092	1			T19	5		T21	1		T31	6
valid_sources[0x19]	21616	1			T19	2		T31	9		T39	13
valid_sources[0x1a]	25840	1			T19	15		T25	1		T31	5
valid_sources[0x1b]	19742	1			T19	6		T25	2		T38	1
valid_sources[0x1c]	103111	1			T19	2		T21	1		T31	8
valid_sources[0x1d]	20299	1			T19	3		T22	1		T25	2
valid_sources[0x1e]	18247	1			T19	4		T21	1		T25	2
valid_sources[0x1f]	21269	1			T19	3		T25	1		T31	8
valid_sources[0x20]	19547	1			T19	9		T21	4		T31	4
valid_sources[0x21]	51259	1			T19	1		T25	2		T31	7
valid_sources[0x22]	20308	1			T19	14		T25	2		T38	1
valid_sources[0x23]	17762	1			T19	5		T38	1		T31	13
valid_sources[0x24]	18284	1			T19	19		T22	2		T24	71
valid_sources[0x25]	60074	1			T19	3		T25	1		T31	4
valid_sources[0x26]	23518	1			T19	14		T25	1		T31	5
valid_sources[0x27]	18410	1			T19	11		T25	2		T31	4
valid_sources[0x28]	25468	1			T19	13		T21	2		T25	1
valid_sources[0x29]	20315	1			T19	15		T21	3		T25	1
valid_sources[0x2a]	21540	1			T19	8		T25	1		T31	5
valid_sources[0x2b]	22750	1			T19	4		T25	1		T31	6
valid_sources[0x2c]	21544	1			T19	22		T25	1		T38	2
valid_sources[0x2d]	18573	1			T19	23		T38	1		T31	11
valid_sources[0x2e]	18093	1			T19	18		T25	1		T31	7
valid_sources[0x2f]	21189	1			T19	26		T31	9		T39	7
valid_sources[0x30]	18492	1			T19	8		T25	3		T31	4
valid_sources[0x31]	18107	1			T19	40		T21	1		T25	1
valid_sources[0x32]	23312	1			T19	21		T25	2		T38	1
valid_sources[0x33]	19097	1			T19	33		T25	4		T31	5
valid_sources[0x34]	71072	1			T19	5		T21	4		T25	1
valid_sources[0x35]	18938	1			T19	14		T25	1		T31	1
valid_sources[0x36]	22300	1			T19	4		T21	1		T31	6
valid_sources[0x37]	22020	1			T19	5		T25	2		T31	4
valid_sources[0x38]	20701	1			T19	9		T22	3		T31	7
valid_sources[0x39]	18717	1			T19	14		T21	1		T25	2
valid_sources[0x3a]	21283	1			T19	11		T31	7		T39	6
valid_sources[0x3b]	18916	1			T19	49		T21	1		T25	2
valid_sources[0x3c]	19524	1			T19	4		T21	2		T25	2
valid_sources[0x3d]	24661	1			T19	10		T38	1		T31	3
valid_sources[0x3e]	18630	1			T25	3		T31	6		T39	6
valid_sources[0x3f]	20988	1			T19	10		T21	3		T25	2
valid_sources[0x40]	20408	1			T19	9		T22	2		T31	4
valid_sources[0x41]	17597	1			T19	2		T21	2		T25	1
valid_sources[0x42]	19217	1			T19	8		T21	2		T25	2
valid_sources[0x43]	19074	1			T19	43		T25	1		T38	1
valid_sources[0x44]	17753	1			T19	11		T21	2		T25	3
valid_sources[0x45]	19351	1			T19	7		T21	3		T25	1
valid_sources[0x46]	20256	1			T19	15		T25	2		T31	5
valid_sources[0x47]	18397	1			T19	16		T21	1		T38	2
valid_sources[0x48]	18011	1			T19	12		T31	7		T39	7
valid_sources[0x49]	18596	1			T19	9		T21	4		T22	1
valid_sources[0x4a]	21165	1			T19	33		T38	1		T31	5
valid_sources[0x4b]	19547	1			T19	29		T21	2		T25	2
valid_sources[0x4c]	18892	1			T19	8		T25	1		T38	1
valid_sources[0x4d]	19492	1			T19	44		T39	9		T29	212
valid_sources[0x4e]	67060	1			T19	31		T31	5		T39	9
valid_sources[0x4f]	19024	1			T19	17		T31	4		T39	4
valid_sources[0x50]	18084	1			T19	6		T22	1		T25	3
valid_sources[0x51]	19152	1			T19	18		T31	4		T39	11
valid_sources[0x52]	20054	1			T19	1		T22	1		T25	1
valid_sources[0x53]	18947	1			T19	7		T25	2		T31	1
valid_sources[0x54]	18811	1			T19	7		T21	1		T25	1
valid_sources[0x55]	18942	1			T19	17		T31	6		T39	6
valid_sources[0x56]	18540	1			T19	9		T25	3		T31	4
valid_sources[0x57]	18446	1			T19	13		T25	1		T31	7
valid_sources[0x58]	18909	1			T19	14		T25	1		T31	4
valid_sources[0x59]	19224	1			T19	21		T21	2		T25	1
valid_sources[0x5a]	18863	1			T19	73		T21	1		T25	3
valid_sources[0x5b]	17909	1			T19	11		T21	2		T25	1
valid_sources[0x5c]	17807	1			T25	1		T31	4		T39	14
valid_sources[0x5d]	20755	1			T19	13		T25	3		T38	1
valid_sources[0x5e]	21293	1			T19	19		T25	1		T38	2
valid_sources[0x5f]	20979	1			T19	13		T21	6		T25	1
valid_sources[0x60]	20425	1			T19	5		T25	2		T31	4
valid_sources[0x61]	19904	1			T19	10		T21	4		T31	2
valid_sources[0x62]	18866	1			T19	3		T22	1		T38	1
valid_sources[0x63]	20745	1			T19	11		T38	1		T31	7
valid_sources[0x64]	19856	1			T19	14		T25	1		T38	2
valid_sources[0x65]	19689	1			T19	20		T21	3		T25	3
valid_sources[0x66]	18797	1			T19	3		T22	1		T25	2
valid_sources[0x67]	21734	1			T19	19		T21	3		T25	1
valid_sources[0x68]	18531	1			T19	12		T21	3		T25	1
valid_sources[0x69]	20979	1			T19	11		T25	1		T38	1
valid_sources[0x6a]	20590	1			T19	10		T25	2		T31	10
valid_sources[0x6b]	21844	1			T19	28		T21	1		T25	2
valid_sources[0x6c]	22858	1			T19	5		T20	4		T31	5
valid_sources[0x6d]	20084	1			T19	6		T23	339		T31	8
valid_sources[0x6e]	24088	1			T19	16		T25	2		T31	8
valid_sources[0x6f]	20875	1			T19	2		T22	1		T31	4
valid_sources[0x70]	19936	1			T25	1		T38	1		T31	5
valid_sources[0x71]	18028	1			T19	2		T21	1		T31	8
valid_sources[0x72]	21781	1			T25	2		T31	5		T39	9
valid_sources[0x73]	21085	1			T19	9		T21	1		T25	3
valid_sources[0x74]	20395	1			T19	4		T25	2		T31	10
valid_sources[0x75]	20946	1			T19	30		T25	4		T38	2
valid_sources[0x76]	27356	1			T19	12		T31	4		T39	14
valid_sources[0x77]	19278	1			T19	54		T21	1		T25	2
valid_sources[0x78]	19777	1			T19	2		T21	2		T22	1
valid_sources[0x79]	19465	1			T19	19		T25	1		T31	8
valid_sources[0x7a]	19445	1			T19	13		T20	5		T25	2
valid_sources[0x7b]	19084	1			T19	22		T31	2		T39	6
valid_sources[0x7c]	18282	1			T19	12		T25	2		T31	9
valid_sources[0x7d]	18243	1			T19	16		T31	2		T39	4
valid_sources[0x7e]	19825	1			T19	16		T21	1		T31	8
valid_sources[0x7f]	19978	1			T19	2		T38	1		T31	6
valid_sources[0x80]	21568	1			T19	1		T25	2		T31	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1319336

1

T19

653

T21

19

T22

2

values[0x0]

all_enables

biggest_size

1582188

1

T19

1106

T20

4

T21

75

values[0x1]

all_enables

biggest_size

1585065

1

T19

1121

T20

3

T21

70