Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	45216386	0	0	0
ctrl_en_input_filter_rd_A	45216386	64174	0	0
intr_ctrl_en_falling_rd_A	45216386	63242	0	0
intr_ctrl_en_lvlhigh_rd_A	45216386	64109	0	0
intr_ctrl_en_lvllow_rd_A	45216386	64409	0	0
intr_ctrl_en_rising_rd_A	45216386	63607	0	0
intr_enable_rd_A	45216386	64315	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	45216386	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	45216386	64174	0	0
T1	400182	1888	0	0
T2	9005	6	0	0
T3	623183	2013	0	0
T4	0	5	0	0
T5	0	5473	0	0
T6	0	3105	0	0
T7	0	276	0	0
T8	0	4186	0	0
T9	0	3987	0	0
T10	0	1783	0	0
T11	2155	0	0	0
T12	7556	0	0	0
T13	2901	0	0	0
T14	802	0	0	0
T15	2493	0	0	0
T16	4468	0	0	0
T17	4850	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	45216386	63242	0	0
T1	400182	1811	0	0
T2	9005	11	0	0
T3	623183	2008	0	0
T5	0	5217	0	0
T6	0	3038	0	0
T7	0	226	0	0
T8	0	4328	0	0
T9	0	3730	0	0
T10	0	1762	0	0
T11	2155	0	0	0
T12	7556	0	0	0
T13	2901	0	0	0
T14	802	0	0	0
T15	2493	0	0	0
T16	4468	0	0	0
T17	4850	0	0	0
T18	0	3494	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	45216386	64109	0	0
T1	400182	1903	0	0
T2	9005	0	0	0
T3	623183	2267	0	0
T4	0	4	0	0
T5	0	5049	0	0
T6	0	3038	0	0
T7	0	257	0	0
T8	0	4096	0	0
T9	0	4019	0	0
T10	0	1731	0	0
T11	2155	0	0	0
T12	7556	0	0	0
T13	2901	0	0	0
T14	802	0	0	0
T15	2493	0	0	0
T16	4468	0	0	0
T17	4850	0	0	0
T18	0	3547	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	45216386	64409	0	0
T1	400182	1840	0	0
T2	9005	11	0	0
T3	623183	2108	0	0
T5	0	5436	0	0
T6	0	2948	0	0
T7	0	261	0	0
T8	0	4059	0	0
T9	0	4130	0	0
T10	0	1921	0	0
T11	2155	0	0	0
T12	7556	0	0	0
T13	2901	0	0	0
T14	802	0	0	0
T15	2493	0	0	0
T16	4468	0	0	0
T17	4850	0	0	0
T18	0	3585	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	45216386	63607	0	0
T1	400182	1704	0	0
T2	9005	0	0	0
T3	623183	2045	0	0
T4	0	22	0	0
T5	0	4760	0	0
T6	0	3202	0	0
T7	0	221	0	0
T8	0	4475	0	0
T9	0	4194	0	0
T10	0	1586	0	0
T11	2155	0	0	0
T12	7556	0	0	0
T13	2901	0	0	0
T14	802	0	0	0
T15	2493	0	0	0
T16	4468	0	0	0
T17	4850	0	0	0
T18	0	3534	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	45216386	64315	0	0
T1	400182	1609	0	0
T2	9005	6	0	0
T3	623183	2192	0	0
T5	0	5276	0	0
T6	0	2942	0	0
T7	0	312	0	0
T8	0	4146	0	0
T9	0	3852	0	0
T10	0	1729	0	0
T11	2155	0	0	0
T12	7556	0	0	0
T13	2901	0	0	0
T14	802	0	0	0
T15	2493	0	0	0
T16	4468	0	0	0
T17	4850	0	0	0
T18	0	3553	0	0