Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1279876	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4500984

1

T25

3325

T26

212

T1

18389

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2596499	1			T25	2065		T26	132		T1	9670
values[0x0]	1588042	1			T25	1157		T26	66		T1	6837
values[0x1]	1596319	1			T25	1146		T26	73		T1	6727

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1017638	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4763222

1

T25

3549

T26

221

T1

19331

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16111	1			T25	42		T11	4		T13	1
valid_sources[0x01]	15811	1			T25	43		T11	1		T13	4
valid_sources[0x02]	16954	1			T25	17		T26	1		T11	1
valid_sources[0x03]	16377	1			T25	14		T26	1		T11	2
valid_sources[0x04]	16429	1			T25	22		T11	2		T13	1
valid_sources[0x05]	16112	1			T25	3		T26	1		T11	1
valid_sources[0x06]	15433	1			T25	13		T11	2		T13	4
valid_sources[0x07]	117054	1			T25	15		T26	2		T13	1
valid_sources[0x08]	18241	1			T25	8		T26	1		T11	1
valid_sources[0x09]	16581	1			T25	25		T26	1		T11	1
valid_sources[0x0a]	15965	1			T25	16		T26	3		T13	3
valid_sources[0x0b]	19196	1			T25	8		T26	1		T11	1
valid_sources[0x0c]	22944	1			T25	12		T26	1		T11	5
valid_sources[0x0d]	15783	1			T25	19		T11	3		T13	7
valid_sources[0x0e]	18401	1			T25	26		T11	3		T15	647
valid_sources[0x0f]	15769	1			T25	28		T11	2		T13	1
valid_sources[0x10]	18533	1			T25	6		T11	2		T13	1
valid_sources[0x11]	24476	1			T25	11		T13	2		T15	572
valid_sources[0x12]	15858	1			T25	12		T26	1		T13	1
valid_sources[0x13]	16631	1			T25	13		T26	4		T11	6
valid_sources[0x14]	19074	1			T25	12		T26	1		T13	2
valid_sources[0x15]	19885	1			T25	1		T11	1		T15	495
valid_sources[0x16]	199512	1			T25	19		T26	2		T11	2
valid_sources[0x17]	15303	1			T25	12		T11	1		T13	1
valid_sources[0x18]	16415	1			T25	5		T11	1		T15	549
valid_sources[0x19]	17887	1			T25	11		T26	1		T11	8
valid_sources[0x1a]	17817	1			T25	22		T11	2		T13	2
valid_sources[0x1b]	18332	1			T25	2		T26	2		T13	2
valid_sources[0x1c]	22823	1			T25	8		T26	1		T11	3
valid_sources[0x1d]	16876	1			T25	18		T26	2		T11	2
valid_sources[0x1e]	16609	1			T25	39		T11	4		T13	3
valid_sources[0x1f]	16953	1			T25	29		T11	3		T13	1
valid_sources[0x20]	15758	1			T25	31		T26	2		T11	5
valid_sources[0x21]	16779	1			T25	7		T11	1		T13	3
valid_sources[0x22]	16279	1			T25	12		T26	1		T11	1
valid_sources[0x23]	15712	1			T25	19		T11	3		T13	1
valid_sources[0x24]	15759	1			T25	10		T26	3		T11	2
valid_sources[0x25]	16008	1			T25	9		T26	2		T13	3
valid_sources[0x26]	179939	1			T25	8		T26	3		T11	2
valid_sources[0x27]	19066	1			T25	3		T11	4		T13	5
valid_sources[0x28]	16334	1			T25	13		T26	1		T11	2
valid_sources[0x29]	17342	1			T25	11		T26	2		T11	4
valid_sources[0x2a]	16570	1			T25	36		T26	3		T11	1
valid_sources[0x2b]	16531	1			T25	16		T15	461		T17	1
valid_sources[0x2c]	16776	1			T25	19		T11	2		T13	1
valid_sources[0x2d]	17634	1			T25	21		T26	1		T11	1
valid_sources[0x2e]	17149	1			T25	4		T11	6		T13	2
valid_sources[0x2f]	17176	1			T25	11		T26	1		T11	3
valid_sources[0x30]	16181	1			T25	14		T26	3		T11	2
valid_sources[0x31]	16981	1			T25	13		T26	2		T11	1
valid_sources[0x32]	15445	1			T25	13		T26	1		T11	3
valid_sources[0x33]	16328	1			T25	44		T26	1		T11	4
valid_sources[0x34]	21605	1			T25	33		T26	1		T11	2
valid_sources[0x35]	19439	1			T25	26		T11	2		T12	1222
valid_sources[0x36]	33205	1			T25	8		T11	2		T13	4
valid_sources[0x37]	16175	1			T25	11		T11	1		T13	4
valid_sources[0x38]	21358	1			T25	23		T26	1		T11	3
valid_sources[0x39]	66572	1			T25	8		T26	3		T11	1
valid_sources[0x3a]	20003	1			T25	18		T26	1		T11	3
valid_sources[0x3b]	16602	1			T25	12		T13	1		T15	553
valid_sources[0x3c]	21293	1			T25	40		T26	3		T11	2
valid_sources[0x3d]	16150	1			T25	14		T13	1		T15	567
valid_sources[0x3e]	15728	1			T25	3		T11	2		T13	3
valid_sources[0x3f]	24919	1			T25	11		T26	2		T11	4
valid_sources[0x40]	15973	1			T25	27		T26	1		T11	2
valid_sources[0x41]	16956	1			T25	19		T26	2		T11	3
valid_sources[0x42]	132528	1			T25	14		T26	2		T11	1
valid_sources[0x43]	17983	1			T25	2		T26	1		T11	2
valid_sources[0x44]	17435	1			T25	10		T26	1		T11	4
valid_sources[0x45]	15647	1			T25	32		T11	3		T13	4
valid_sources[0x46]	15941	1			T25	41		T11	2		T13	1
valid_sources[0x47]	16822	1			T25	32		T26	1		T11	3
valid_sources[0x48]	17684	1			T25	3		T26	1		T11	2
valid_sources[0x49]	17776	1			T25	8		T11	3		T13	1
valid_sources[0x4a]	16200	1			T25	22		T26	1		T11	1
valid_sources[0x4b]	16984	1			T25	7		T26	1		T11	3
valid_sources[0x4c]	16431	1			T25	8		T26	5		T11	1
valid_sources[0x4d]	18115	1			T25	11		T13	5		T15	509
valid_sources[0x4e]	20117	1			T25	19		T26	2		T11	1
valid_sources[0x4f]	141766	1			T25	5		T11	6		T13	4
valid_sources[0x50]	16715	1			T25	6		T26	3		T11	1
valid_sources[0x51]	16424	1			T25	30		T13	2		T15	527
valid_sources[0x52]	17215	1			T25	36		T26	2		T11	2
valid_sources[0x53]	19210	1			T25	9		T11	1		T13	2
valid_sources[0x54]	16448	1			T25	7		T13	4		T15	572
valid_sources[0x55]	19962	1			T25	12		T26	1		T11	3
valid_sources[0x56]	18164	1			T25	21		T11	3		T13	3
valid_sources[0x57]	18586	1			T25	19		T11	2		T13	1
valid_sources[0x58]	17498	1			T25	13		T26	2		T11	2
valid_sources[0x59]	16936	1			T25	5		T11	2		T13	2
valid_sources[0x5a]	18234	1			T25	16		T26	2		T11	1
valid_sources[0x5b]	16445	1			T25	23		T26	3		T11	1
valid_sources[0x5c]	15919	1			T25	5		T26	1		T11	4
valid_sources[0x5d]	16700	1			T25	14		T26	1		T11	1
valid_sources[0x5e]	21679	1			T25	2		T11	1		T13	4
valid_sources[0x5f]	16953	1			T25	13		T26	2		T11	5
valid_sources[0x60]	17497	1			T25	25		T26	1		T11	2
valid_sources[0x61]	16926	1			T25	7		T11	2		T13	1
valid_sources[0x62]	16220	1			T25	6		T26	1		T13	1
valid_sources[0x63]	17336	1			T25	21		T26	2		T11	3
valid_sources[0x64]	16233	1			T25	30		T26	1		T11	2
valid_sources[0x65]	15850	1			T25	3		T11	4		T13	1
valid_sources[0x66]	21737	1			T25	13		T26	2		T11	1
valid_sources[0x67]	18098	1			T25	10		T26	1		T11	5
valid_sources[0x68]	16131	1			T25	27		T11	3		T13	3
valid_sources[0x69]	15928	1			T25	1		T26	1		T11	1
valid_sources[0x6a]	16953	1			T25	4		T26	1		T11	2
valid_sources[0x6b]	16463	1			T25	5		T26	1		T11	5
valid_sources[0x6c]	15934	1			T25	29		T26	1		T11	1
valid_sources[0x6d]	17536	1			T25	35		T11	3		T13	2
valid_sources[0x6e]	22304	1			T25	16		T11	2		T13	1
valid_sources[0x6f]	18570	1			T25	15		T26	2		T11	1
valid_sources[0x70]	16306	1			T25	16		T26	1		T11	1
valid_sources[0x71]	17683	1			T25	31		T26	1		T11	3
valid_sources[0x72]	18533	1			T25	23		T26	2		T11	1
valid_sources[0x73]	15588	1			T25	3		T26	1		T11	4
valid_sources[0x74]	16125	1			T25	2		T11	3		T13	3
valid_sources[0x75]	16368	1			T25	27		T13	3		T15	472
valid_sources[0x76]	15966	1			T25	25		T26	1		T11	2
valid_sources[0x77]	17107	1			T25	15		T26	2		T11	2
valid_sources[0x78]	41579	1			T25	15		T1	23234		T11	1
valid_sources[0x79]	16070	1			T25	18		T26	1		T13	3
valid_sources[0x7a]	18986	1			T25	20		T26	1		T11	3
valid_sources[0x7b]	17457	1			T25	5		T26	2		T13	3
valid_sources[0x7c]	15667	1			T25	35		T11	2		T13	5
valid_sources[0x7d]	16306	1			T25	12		T11	2		T13	1
valid_sources[0x7e]	16400	1			T25	5		T26	1		T11	2
valid_sources[0x7f]	16801	1			T25	12		T11	4		T13	2
valid_sources[0x80]	19179	1			T25	4		T26	1		T11	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1330429

1

T25

1022

T26

73

T1

4825

values[0x0]

all_enables

biggest_size

1586505

1

T25

1157

T26

66

T1

6837

values[0x1]

all_enables

biggest_size

1584050

1

T25

1146

T26

73

T1

6727