Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	48389600	0	0	0
ctrl_en_input_filter_rd_A	48389600	60751	0	0
intr_ctrl_en_falling_rd_A	48389600	61438	0	0
intr_ctrl_en_lvlhigh_rd_A	48389600	61449	0	0
intr_ctrl_en_lvllow_rd_A	48389600	62582	0	0
intr_ctrl_en_rising_rd_A	48389600	61174	0	0
intr_enable_rd_A	48389600	62980	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48389600	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48389600	60751	0	0
T1	329802	806	0	0
T2	0	67	0	0
T3	0	2407	0	0
T4	0	2134	0	0
T5	0	226	0	0
T6	0	1742	0	0
T7	0	6	0	0
T8	0	4607	0	0
T9	0	3282	0	0
T10	0	122	0	0
T11	4376	0	0	0
T12	5133	0	0	0
T13	8356	0	0	0
T14	1429	0	0	0
T15	648239	0	0	0
T16	5775	0	0	0
T17	8455	0	0	0
T18	3432	0	0	0
T19	22057	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48389600	61438	0	0
T1	329802	737	0	0
T2	0	83	0	0
T3	0	2566	0	0
T4	0	2281	0	0
T5	0	154	0	0
T6	0	1978	0	0
T8	0	4604	0	0
T9	0	3205	0	0
T10	0	139	0	0
T11	4376	0	0	0
T12	5133	0	0	0
T13	8356	0	0	0
T14	1429	0	0	0
T15	648239	0	0	0
T16	5775	0	0	0
T17	8455	0	0	0
T18	3432	0	0	0
T19	22057	0	0	0
T20	0	3	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48389600	61449	0	0
T1	329802	776	0	0
T2	0	59	0	0
T3	0	2354	0	0
T4	0	2255	0	0
T5	0	138	0	0
T6	0	1616	0	0
T8	0	5044	0	0
T9	0	3138	0	0
T11	4376	0	0	0
T12	5133	0	0	0
T13	8356	0	0	0
T14	1429	0	0	0
T15	648239	0	0	0
T16	5775	0	0	0
T17	8455	0	0	0
T18	3432	0	0	0
T19	22057	0	0	0
T21	0	1	0	0
T22	0	1	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48389600	62582	0	0
T1	329802	881	0	0
T2	0	70	0	0
T3	0	2396	0	0
T4	0	2351	0	0
T5	0	174	0	0
T6	0	1815	0	0
T8	0	4654	0	0
T11	4376	0	0	0
T12	5133	0	0	0
T13	8356	0	0	0
T14	1429	0	0	0
T15	648239	0	0	0
T16	5775	0	0	0
T17	8455	0	0	0
T18	3432	0	0	0
T19	22057	0	0	0
T20	0	1	0	0
T21	0	6	0	0
T23	0	6	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48389600	61174	0	0
T1	329802	724	0	0
T2	0	56	0	0
T3	0	2479	0	0
T4	0	2104	0	0
T5	0	240	0	0
T6	0	1691	0	0
T8	0	5033	0	0
T9	0	3287	0	0
T10	0	141	0	0
T11	4376	0	0	0
T12	5133	0	0	0
T13	8356	0	0	0
T14	1429	0	0	0
T15	648239	0	0	0
T16	5775	0	0	0
T17	8455	0	0	0
T18	3432	0	0	0
T19	22057	0	0	0
T24	0	193	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48389600	62980	0	0
T1	329802	678	0	0
T2	0	47	0	0
T3	0	2606	0	0
T4	0	2244	0	0
T5	0	206	0	0
T6	0	1752	0	0
T7	0	5	0	0
T8	0	5104	0	0
T9	0	3590	0	0
T10	0	110	0	0
T11	4376	0	0	0
T12	5133	0	0	0
T13	8356	0	0	0
T14	1429	0	0	0
T15	648239	0	0	0
T16	5775	0	0	0
T17	8455	0	0	0
T18	3432	0	0	0
T19	22057	0	0	0