Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1435554	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5049874

1

T22

338

T23

315

T24

158

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2911354	1			T22	174		T23	65		T24	141
values[0x0]	1782723	1			T22	146		T23	148		T24	42
values[0x1]	1791351	1			T22	110		T23	139		T24	44

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1141340	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5344088

1

T22

350

T23

321

T24

169

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	20047	1			T22	2		T23	1		T1	4
valid_sources[0x01]	23516	1			T23	1		T1	8		T12	2
valid_sources[0x02]	22662	1			T1	2		T13	4		T14	6
valid_sources[0x03]	19254	1			T22	2		T23	3		T1	3
valid_sources[0x04]	22275	1			T23	1		T24	17		T25	8
valid_sources[0x05]	19286	1			T22	2		T23	2		T1	8
valid_sources[0x06]	21974	1			T22	2		T23	1		T1	22
valid_sources[0x07]	19661	1			T22	2		T1	13		T12	2
valid_sources[0x08]	19769	1			T22	1		T25	3		T1	7
valid_sources[0x09]	21182	1			T22	3		T1	19		T12	2
valid_sources[0x0a]	25099	1			T22	1		T1	27		T12	2
valid_sources[0x0b]	23889	1			T23	1		T1	1		T12	5
valid_sources[0x0c]	21827	1			T22	2		T1	15		T12	1
valid_sources[0x0d]	18784	1			T23	1		T1	10		T12	1
valid_sources[0x0e]	21686	1			T23	1		T1	34		T12	3
valid_sources[0x0f]	20220	1			T22	2		T24	58		T1	17
valid_sources[0x10]	19697	1			T22	3		T23	1		T1	5
valid_sources[0x11]	20111	1			T22	1		T23	1		T1	10
valid_sources[0x12]	20225	1			T22	1		T23	3		T1	12
valid_sources[0x13]	19945	1			T22	2		T1	3		T12	1
valid_sources[0x14]	19901	1			T22	2		T23	2		T26	16
valid_sources[0x15]	26335	1			T23	4		T1	14		T12	2
valid_sources[0x16]	24305	1			T22	3		T1	9		T12	1
valid_sources[0x17]	19717	1			T22	1		T25	13		T1	1
valid_sources[0x18]	25166	1			T22	1		T23	2		T26	2
valid_sources[0x19]	22146	1			T22	2		T23	1		T1	7
valid_sources[0x1a]	23246	1			T22	5		T23	2		T1	9
valid_sources[0x1b]	20457	1			T22	3		T1	14		T13	4
valid_sources[0x1c]	19814	1			T22	4		T23	2		T1	24
valid_sources[0x1d]	19717	1			T22	6		T23	2		T1	9
valid_sources[0x1e]	20417	1			T22	5		T23	1		T1	10
valid_sources[0x1f]	19368	1			T23	2		T25	2		T1	1
valid_sources[0x20]	23184	1			T22	1		T23	2		T1	14
valid_sources[0x21]	21302	1			T22	2		T1	5		T12	1
valid_sources[0x22]	19262	1			T22	3		T23	3		T1	3
valid_sources[0x23]	25907	1			T22	1		T23	4		T1	4
valid_sources[0x24]	19749	1			T22	2		T1	21		T13	8
valid_sources[0x25]	20739	1			T23	2		T1	5		T13	8
valid_sources[0x26]	19750	1			T23	1		T1	9		T13	10
valid_sources[0x27]	20074	1			T22	1		T1	8		T12	1
valid_sources[0x28]	19006	1			T22	1		T23	1		T1	3
valid_sources[0x29]	22290	1			T22	1		T23	2		T1	4
valid_sources[0x2a]	19828	1			T22	2		T23	3		T1	9
valid_sources[0x2b]	19408	1			T22	3		T23	2		T1	3
valid_sources[0x2c]	19833	1			T22	4		T23	2		T1	11
valid_sources[0x2d]	72533	1			T22	2		T23	3		T1	33
valid_sources[0x2e]	24827	1			T22	2		T23	2		T24	8
valid_sources[0x2f]	27038	1			T22	2		T23	1		T1	16
valid_sources[0x30]	22789	1			T23	1		T1	15		T13	23
valid_sources[0x31]	20300	1			T22	2		T23	2		T1	10
valid_sources[0x32]	24713	1			T1	26		T12	1		T13	21
valid_sources[0x33]	19311	1			T22	3		T23	1		T1	24
valid_sources[0x34]	23673	1			T23	1		T1	22		T13	14
valid_sources[0x35]	19865	1			T23	3		T1	25		T13	2
valid_sources[0x36]	19151	1			T23	1		T25	7		T1	6
valid_sources[0x37]	19641	1			T23	1		T1	23		T13	15
valid_sources[0x38]	20150	1			T22	1		T23	2		T1	24
valid_sources[0x39]	28972	1			T22	2		T23	1		T1	7
valid_sources[0x3a]	18987	1			T22	1		T23	2		T1	21
valid_sources[0x3b]	19076	1			T22	1		T23	2		T25	17
valid_sources[0x3c]	21650	1			T22	5		T23	1		T1	28
valid_sources[0x3d]	21607	1			T22	2		T23	3		T24	9
valid_sources[0x3e]	20284	1			T22	5		T1	4		T12	2
valid_sources[0x3f]	18896	1			T22	5		T23	3		T1	4
valid_sources[0x40]	18417	1			T22	3		T26	42		T1	12
valid_sources[0x41]	21294	1			T22	4		T23	1		T25	25
valid_sources[0x42]	19556	1			T23	1		T1	15		T12	2
valid_sources[0x43]	22138	1			T23	1		T1	31		T13	17
valid_sources[0x44]	21869	1			T22	1		T23	2		T25	4
valid_sources[0x45]	20007	1			T22	1		T1	7		T12	1
valid_sources[0x46]	20103	1			T22	1		T23	2		T1	3
valid_sources[0x47]	19661	1			T22	6		T1	26		T13	5
valid_sources[0x48]	19111	1			T22	3		T23	1		T1	26
valid_sources[0x49]	19177	1			T1	5		T13	3		T14	2
valid_sources[0x4a]	19537	1			T22	2		T23	2		T1	16
valid_sources[0x4b]	18531	1			T22	2		T23	1		T1	7
valid_sources[0x4c]	20267	1			T22	3		T1	34		T12	4
valid_sources[0x4d]	21102	1			T22	3		T1	6		T13	12
valid_sources[0x4e]	19993	1			T22	3		T23	2		T1	10
valid_sources[0x4f]	26683	1			T22	3		T23	1		T1	3
valid_sources[0x50]	91876	1			T22	1		T23	2		T1	28
valid_sources[0x51]	23113	1			T22	1		T23	2		T1	25
valid_sources[0x52]	19062	1			T22	1		T25	8		T1	14
valid_sources[0x53]	21014	1			T22	1		T23	1		T1	12
valid_sources[0x54]	20670	1			T22	2		T23	1		T25	20
valid_sources[0x55]	132356	1			T26	11		T1	23		T12	3
valid_sources[0x56]	22337	1			T23	1		T1	20		T12	1
valid_sources[0x57]	42152	1			T22	3		T23	2		T1	17
valid_sources[0x58]	19043	1			T22	1		T23	1		T1	10
valid_sources[0x59]	19278	1			T22	2		T23	3		T1	14
valid_sources[0x5a]	19801	1			T22	2		T23	1		T12	1
valid_sources[0x5b]	28232	1			T22	1		T23	1		T1	19
valid_sources[0x5c]	20579	1			T23	3		T1	7		T12	3
valid_sources[0x5d]	22278	1			T22	5		T23	1		T26	7
valid_sources[0x5e]	20729	1			T23	3		T25	6		T12	3
valid_sources[0x5f]	21947	1			T22	1		T1	20		T12	1
valid_sources[0x60]	19978	1			T22	8		T23	1		T1	9
valid_sources[0x61]	22445	1			T26	25		T1	4		T13	8
valid_sources[0x62]	19597	1			T22	1		T23	4		T1	22
valid_sources[0x63]	20822	1			T22	1		T23	1		T1	7
valid_sources[0x64]	28017	1			T22	1		T1	38		T13	14
valid_sources[0x65]	21191	1			T22	2		T23	2		T1	14
valid_sources[0x66]	22391	1			T23	2		T25	12		T1	9
valid_sources[0x67]	19913	1			T1	23		T13	46		T14	3
valid_sources[0x68]	19107	1			T22	1		T23	2		T1	8
valid_sources[0x69]	20720	1			T23	2		T1	7		T12	2
valid_sources[0x6a]	19681	1			T22	2		T23	2		T1	8
valid_sources[0x6b]	21548	1			T23	3		T25	11		T1	9
valid_sources[0x6c]	20293	1			T22	1		T1	17		T13	5
valid_sources[0x6d]	20096	1			T22	5		T24	2		T25	12
valid_sources[0x6e]	23206	1			T22	1		T23	1		T1	26
valid_sources[0x6f]	19129	1			T22	1		T23	3		T1	44
valid_sources[0x70]	21418	1			T22	5		T25	1		T1	20
valid_sources[0x71]	19777	1			T22	1		T23	1		T24	14
valid_sources[0x72]	22276	1			T22	1		T23	2		T1	9
valid_sources[0x73]	20682	1			T1	8		T13	12		T14	1
valid_sources[0x74]	19510	1			T23	2		T1	11		T12	1
valid_sources[0x75]	22657	1			T22	1		T23	1		T1	13
valid_sources[0x76]	19653	1			T22	2		T23	1		T1	2
valid_sources[0x77]	21868	1			T22	1		T1	3		T12	4
valid_sources[0x78]	23476	1			T22	3		T23	2		T1	10
valid_sources[0x79]	19913	1			T23	4		T24	8		T26	1
valid_sources[0x7a]	19492	1			T22	1		T1	8		T12	2
valid_sources[0x7b]	20490	1			T22	1		T23	2		T1	2
valid_sources[0x7c]	21185	1			T22	2		T23	2		T1	5
valid_sources[0x7d]	20706	1			T22	1		T24	19		T1	5
valid_sources[0x7e]	19315	1			T22	1		T1	4		T12	2
valid_sources[0x7f]	21953	1			T22	3		T1	12		T12	1
valid_sources[0x80]	20695	1			T22	5		T23	3		T1	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1490756

1

T22

82

T23

28

T24

72

values[0x0]

all_enables

biggest_size

1781045

1

T22

146

T23

148

T24

42

values[0x1]

all_enables

biggest_size

1778073

1

T22

110

T23

139

T24

44