Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	50515199	0	0	0
ctrl_en_input_filter_rd_A	50515199	50801	0	0
intr_ctrl_en_falling_rd_A	50515199	50419	0	0
intr_ctrl_en_lvlhigh_rd_A	50515199	52017	0	0
intr_ctrl_en_lvllow_rd_A	50515199	51110	0	0
intr_ctrl_en_rising_rd_A	50515199	50797	0	0
intr_enable_rd_A	50515199	51578	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50515199	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50515199	50801	0	0
T1	37089	256	0	0
T2	0	1938	0	0
T3	0	21	0	0
T4	0	16	0	0
T5	0	6	0	0
T6	0	1054	0	0
T7	0	389	0	0
T8	0	4374	0	0
T9	0	84	0	0
T10	0	243	0	0
T11	1015	0	0	0
T12	6842	0	0	0
T13	19672	0	0	0
T14	7764	0	0	0
T15	8870	0	0	0
T16	8763	0	0	0
T17	8198	0	0	0
T18	6935	0	0	0
T19	7070	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50515199	50419	0	0
T1	37089	188	0	0
T2	0	2111	0	0
T3	0	11	0	0
T4	0	15	0	0
T6	0	1097	0	0
T7	0	371	0	0
T8	0	4625	0	0
T9	0	120	0	0
T10	0	289	0	0
T11	1015	0	0	0
T12	6842	2	0	0
T13	19672	0	0	0
T14	7764	0	0	0
T15	8870	0	0	0
T16	8763	0	0	0
T17	8198	0	0	0
T18	6935	0	0	0
T19	7070	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50515199	52017	0	0
T1	37089	277	0	0
T2	0	2314	0	0
T3	0	34	0	0
T4	0	34	0	0
T6	0	1172	0	0
T7	0	340	0	0
T8	0	4587	0	0
T9	0	86	0	0
T10	0	218	0	0
T11	1015	0	0	0
T12	6842	0	0	0
T13	19672	0	0	0
T14	7764	0	0	0
T15	8870	0	0	0
T16	8763	0	0	0
T17	8198	0	0	0
T18	6935	0	0	0
T19	7070	0	0	0
T20	0	8	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50515199	51110	0	0
T1	37089	228	0	0
T2	0	2188	0	0
T3	0	39	0	0
T4	0	61	0	0
T6	0	1085	0	0
T7	0	370	0	0
T8	0	4621	0	0
T9	0	130	0	0
T10	0	232	0	0
T11	1015	0	0	0
T12	6842	0	0	0
T13	19672	0	0	0
T14	7764	0	0	0
T15	8870	0	0	0
T16	8763	0	0	0
T17	8198	0	0	0
T18	6935	0	0	0
T19	7070	0	0	0
T21	0	3253	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50515199	50797	0	0
T1	37089	219	0	0
T2	0	2265	0	0
T3	0	10	0	0
T4	0	36	0	0
T6	0	955	0	0
T7	0	324	0	0
T8	0	5070	0	0
T9	0	79	0	0
T10	0	244	0	0
T11	1015	0	0	0
T12	6842	0	0	0
T13	19672	0	0	0
T14	7764	0	0	0
T15	8870	0	0	0
T16	8763	0	0	0
T17	8198	0	0	0
T18	6935	0	0	0
T19	7070	0	0	0
T21	0	3589	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50515199	51578	0	0
T1	37089	268	0	0
T2	0	2238	0	0
T3	0	19	0	0
T4	0	59	0	0
T6	0	1134	0	0
T7	0	445	0	0
T8	0	4578	0	0
T9	0	69	0	0
T10	0	267	0	0
T11	1015	0	0	0
T12	6842	0	0	0
T13	19672	0	0	0
T14	7764	0	0	0
T15	8870	0	0	0
T16	8763	0	0	0
T17	8198	0	0	0
T18	6935	0	0	0
T19	7070	0	0	0
T21	0	3289	0	0