Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1295010	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4578806

1

T25

2162

T26

169

T27

24

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2639186	1			T25	3358		T26	111		T27	16
values[0x0]	1611758	1			T25	298		T26	58		T27	7
values[0x1]	1622872	1			T25	251		T26	57		T27	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1027864	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4845952

1

T25

2505

T26

179

T27

25

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15799	1			T25	18		T1	352		T13	15
valid_sources[0x01]	24358	1			T25	5		T26	1		T1	327
valid_sources[0x02]	17894	1			T25	21		T26	1		T1	358
valid_sources[0x03]	17459	1			T25	12		T1	378		T14	6
valid_sources[0x04]	23359	1			T25	9		T26	1		T1	392
valid_sources[0x05]	18796	1			T25	9		T1	333		T13	28
valid_sources[0x06]	25142	1			T25	2		T26	1		T1	372
valid_sources[0x07]	17694	1			T25	12		T26	2		T1	342
valid_sources[0x08]	16462	1			T25	14		T26	1		T27	1
valid_sources[0x09]	19997	1			T25	16		T26	1		T1	348
valid_sources[0x0a]	15890	1			T25	17		T26	1		T1	340
valid_sources[0x0b]	27198	1			T25	37		T27	2		T1	327
valid_sources[0x0c]	29812	1			T25	10		T26	2		T1	406
valid_sources[0x0d]	20597	1			T25	6		T26	1		T1	382
valid_sources[0x0e]	22182	1			T25	8		T1	442		T14	10
valid_sources[0x0f]	23056	1			T25	28		T1	350		T14	21
valid_sources[0x10]	20069	1			T25	30		T26	1		T1	334
valid_sources[0x11]	22068	1			T1	353		T11	1		T14	11
valid_sources[0x12]	19160	1			T25	10		T26	2		T1	307
valid_sources[0x13]	73949	1			T25	19		T28	11		T1	362
valid_sources[0x14]	17557	1			T25	15		T26	1		T1	415
valid_sources[0x15]	22721	1			T25	18		T26	1		T1	366
valid_sources[0x16]	18677	1			T25	22		T26	1		T1	365
valid_sources[0x17]	17350	1			T25	13		T28	18		T1	401
valid_sources[0x18]	27302	1			T25	11		T1	380		T14	4
valid_sources[0x19]	16521	1			T25	14		T1	360		T14	9
valid_sources[0x1a]	22666	1			T25	22		T26	2		T1	349
valid_sources[0x1b]	16523	1			T25	6		T26	1		T1	422
valid_sources[0x1c]	18592	1			T25	21		T26	1		T1	334
valid_sources[0x1d]	15706	1			T25	22		T1	403		T11	1
valid_sources[0x1e]	17857	1			T25	24		T26	1		T27	1
valid_sources[0x1f]	19433	1			T25	9		T1	375		T14	27
valid_sources[0x20]	20574	1			T25	11		T28	1		T1	387
valid_sources[0x21]	15561	1			T25	19		T26	1		T27	2
valid_sources[0x22]	16012	1			T25	30		T26	1		T27	2
valid_sources[0x23]	16346	1			T25	21		T26	2		T1	367
valid_sources[0x24]	23109	1			T25	10		T26	2		T27	1
valid_sources[0x25]	19849	1			T25	24		T26	2		T1	346
valid_sources[0x26]	18190	1			T25	18		T26	3		T1	413
valid_sources[0x27]	18560	1			T25	21		T1	374		T17	1
valid_sources[0x28]	23394	1			T25	6		T1	387		T11	1
valid_sources[0x29]	25050	1			T25	8		T1	353		T14	1
valid_sources[0x2a]	19451	1			T25	20		T1	418		T14	2
valid_sources[0x2b]	21002	1			T25	12		T26	3		T28	6
valid_sources[0x2c]	23879	1			T25	20		T1	377		T11	2
valid_sources[0x2d]	26007	1			T25	28		T1	368		T14	4
valid_sources[0x2e]	16603	1			T25	3		T26	2		T1	363
valid_sources[0x2f]	26752	1			T25	6		T1	369		T14	9
valid_sources[0x30]	18108	1			T25	5		T26	2		T1	399
valid_sources[0x31]	23838	1			T25	15		T26	1		T1	394
valid_sources[0x32]	23641	1			T25	11		T1	404		T17	3
valid_sources[0x33]	20134	1			T25	14		T1	395		T11	1
valid_sources[0x34]	18629	1			T25	10		T26	1		T1	354
valid_sources[0x35]	15290	1			T25	18		T1	343		T14	16
valid_sources[0x36]	17052	1			T25	27		T26	1		T28	2
valid_sources[0x37]	17324	1			T25	19		T1	420		T13	3
valid_sources[0x38]	16381	1			T25	30		T26	1		T1	403
valid_sources[0x39]	18941	1			T25	23		T1	331		T14	18
valid_sources[0x3a]	21862	1			T25	9		T1	350		T13	10
valid_sources[0x3b]	182035	1			T25	17		T26	1		T1	325
valid_sources[0x3c]	17472	1			T25	23		T28	1		T1	380
valid_sources[0x3d]	20155	1			T25	19		T26	2		T1	360
valid_sources[0x3e]	37685	1			T25	2		T26	1		T1	347
valid_sources[0x3f]	17435	1			T25	9		T26	1		T1	386
valid_sources[0x40]	22516	1			T25	18		T28	12		T1	357
valid_sources[0x41]	18815	1			T25	23		T1	388		T11	1
valid_sources[0x42]	19206	1			T25	11		T1	379		T11	3
valid_sources[0x43]	16433	1			T25	19		T26	1		T1	330
valid_sources[0x44]	19266	1			T25	20		T27	3		T1	351
valid_sources[0x45]	16987	1			T25	31		T1	375		T14	15
valid_sources[0x46]	19489	1			T25	13		T26	2		T28	4
valid_sources[0x47]	22813	1			T25	6		T27	1		T1	371
valid_sources[0x48]	19298	1			T25	23		T1	388		T14	19
valid_sources[0x49]	16538	1			T25	4		T1	346		T14	1
valid_sources[0x4a]	17321	1			T25	9		T26	1		T1	374
valid_sources[0x4b]	25328	1			T25	5		T26	1		T1	365
valid_sources[0x4c]	16604	1			T25	4		T26	2		T1	404
valid_sources[0x4d]	17002	1			T25	9		T26	2		T28	10
valid_sources[0x4e]	17432	1			T25	16		T1	393		T11	1
valid_sources[0x4f]	17724	1			T25	10		T1	387		T14	25
valid_sources[0x50]	15996	1			T25	3		T26	3		T1	373
valid_sources[0x51]	19700	1			T25	16		T26	1		T1	380
valid_sources[0x52]	16786	1			T25	19		T26	1		T27	1
valid_sources[0x53]	20448	1			T25	5		T1	388		T14	10
valid_sources[0x54]	15302	1			T25	13		T26	1		T1	394
valid_sources[0x55]	19506	1			T25	13		T26	1		T1	409
valid_sources[0x56]	21842	1			T25	16		T26	2		T1	389
valid_sources[0x57]	21329	1			T25	18		T27	1		T1	377
valid_sources[0x58]	16432	1			T25	8		T26	1		T1	342
valid_sources[0x59]	20747	1			T25	4		T26	2		T1	400
valid_sources[0x5a]	27557	1			T25	5		T26	2		T1	393
valid_sources[0x5b]	20955	1			T25	12		T26	1		T1	424
valid_sources[0x5c]	16980	1			T25	18		T1	401		T14	10
valid_sources[0x5d]	21916	1			T25	10		T26	1		T1	356
valid_sources[0x5e]	18154	1			T25	14		T1	376		T14	1
valid_sources[0x5f]	17811	1			T25	9		T1	356		T14	12
valid_sources[0x60]	15751	1			T25	8		T26	1		T1	405
valid_sources[0x61]	21236	1			T25	10		T26	1		T1	388
valid_sources[0x62]	19237	1			T25	10		T1	315		T13	3
valid_sources[0x63]	19566	1			T25	30		T26	1		T1	395
valid_sources[0x64]	18395	1			T25	13		T26	2		T1	393
valid_sources[0x65]	19430	1			T25	20		T26	1		T1	383
valid_sources[0x66]	20043	1			T25	38		T26	1		T1	369
valid_sources[0x67]	17615	1			T25	23		T1	375		T14	12
valid_sources[0x68]	17051	1			T25	9		T1	393		T14	19
valid_sources[0x69]	18394	1			T25	15		T26	1		T1	377
valid_sources[0x6a]	71212	1			T25	16		T1	370		T14	4
valid_sources[0x6b]	16349	1			T25	12		T1	422		T14	2
valid_sources[0x6c]	17337	1			T25	16		T1	349		T14	8
valid_sources[0x6d]	18197	1			T25	14		T26	3		T1	327
valid_sources[0x6e]	18332	1			T25	12		T26	2		T1	312
valid_sources[0x6f]	21958	1			T25	8		T26	2		T1	399
valid_sources[0x70]	16528	1			T25	16		T26	1		T27	2
valid_sources[0x71]	94143	1			T25	18		T27	1		T1	360
valid_sources[0x72]	23566	1			T25	29		T26	1		T1	397
valid_sources[0x73]	17324	1			T25	11		T26	1		T1	347
valid_sources[0x74]	19721	1			T25	13		T26	4		T1	433
valid_sources[0x75]	16747	1			T25	11		T26	1		T1	349
valid_sources[0x76]	16921	1			T25	6		T1	431		T14	16
valid_sources[0x77]	21296	1			T25	12		T1	358		T14	8
valid_sources[0x78]	18512	1			T25	16		T26	1		T28	1
valid_sources[0x79]	21921	1			T25	5		T26	2		T1	439
valid_sources[0x7a]	22721	1			T25	19		T1	341		T14	17
valid_sources[0x7b]	24266	1			T25	25		T1	403		T11	1
valid_sources[0x7c]	21912	1			T25	13		T26	1		T27	1
valid_sources[0x7d]	16725	1			T25	23		T26	1		T27	1
valid_sources[0x7e]	21024	1			T25	12		T1	358		T14	12
valid_sources[0x7f]	18864	1			T25	13		T1	390		T14	33
valid_sources[0x80]	20748	1			T25	11		T27	1		T1	373

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1361176

1

T25

1613

T26

54

T27

5

values[0x0]

all_enables

biggest_size

1609926

1

T25

298

T26

58

T27

7

values[0x1]

all_enables

biggest_size

1607704

1

T25

251

T26

57

T27

12