Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	43448504	0	0	0
ctrl_en_input_filter_rd_A	43448504	47828	0	0
intr_ctrl_en_falling_rd_A	43448504	48507	0	0
intr_ctrl_en_lvlhigh_rd_A	43448504	47771	0	0
intr_ctrl_en_lvllow_rd_A	43448504	48437	0	0
intr_ctrl_en_rising_rd_A	43448504	48028	0	0
intr_enable_rd_A	43448504	48942	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43448504	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43448504	47828	0	0
T1	125669	4726	0	0
T2	0	4	0	0
T3	0	1	0	0
T4	0	1030	0	0
T5	0	181	0	0
T6	0	121	0	0
T7	0	1423	0	0
T8	0	4	0	0
T9	0	267	0	0
T10	0	350	0	0
T11	2011	0	0	0
T12	8374	0	0	0
T13	2573	0	0	0
T14	50008	0	0	0
T15	4733	0	0	0
T16	2181	0	0	0
T17	8197	0	0	0
T18	8153	0	0	0
T19	3286	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43448504	48507	0	0
T1	125669	4768	0	0
T3	0	2	0	0
T4	0	1103	0	0
T5	0	142	0	0
T6	0	133	0	0
T7	0	1534	0	0
T9	0	271	0	0
T10	0	354	0	0
T11	2011	0	0	0
T12	8374	0	0	0
T13	2573	0	0	0
T14	50008	0	0	0
T15	4733	0	0	0
T16	2181	0	0	0
T17	8197	0	0	0
T18	8153	0	0	0
T19	3286	0	0	0
T20	0	4	0	0
T21	0	171	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43448504	47771	0	0
T1	125669	4786	0	0
T3	0	10	0	0
T4	0	973	0	0
T5	0	112	0	0
T6	0	176	0	0
T7	0	1518	0	0
T9	0	279	0	0
T10	0	364	0	0
T11	2011	0	0	0
T12	8374	0	0	0
T13	2573	0	0	0
T14	50008	0	0	0
T15	4733	0	0	0
T16	2181	0	0	0
T17	8197	0	0	0
T18	8153	0	0	0
T19	3286	0	0	0
T20	0	4	0	0
T22	0	7	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43448504	48437	0	0
T1	125669	5160	0	0
T2	0	2	0	0
T4	0	1014	0	0
T5	0	116	0	0
T6	0	178	0	0
T7	0	1335	0	0
T9	0	226	0	0
T10	0	431	0	0
T11	2011	0	0	0
T12	8374	0	0	0
T13	2573	0	0	0
T14	50008	0	0	0
T15	4733	0	0	0
T16	2181	0	0	0
T17	8197	0	0	0
T18	8153	0	0	0
T19	3286	0	0	0
T21	0	236	0	0
T22	0	2	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43448504	48028	0	0
T1	125669	4957	0	0
T4	0	1148	0	0
T5	0	127	0	0
T6	0	153	0	0
T7	0	1488	0	0
T8	0	19	0	0
T9	0	302	0	0
T10	0	371	0	0
T11	2011	0	0	0
T12	8374	0	0	0
T13	2573	0	0	0
T14	50008	0	0	0
T15	4733	0	0	0
T16	2181	0	0	0
T17	8197	0	0	0
T18	8153	0	0	0
T19	3286	0	0	0
T22	0	4	0	0
T23	0	4	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43448504	48942	0	0
T1	125669	4965	0	0
T4	0	925	0	0
T5	0	119	0	0
T6	0	91	0	0
T7	0	1604	0	0
T8	0	14	0	0
T9	0	258	0	0
T10	0	460	0	0
T11	2011	0	0	0
T12	8374	0	0	0
T13	2573	0	0	0
T14	50008	0	0	0
T15	4733	0	0	0
T16	2181	0	0	0
T17	8197	0	0	0
T18	8153	0	0	0
T19	3286	0	0	0
T21	0	209	0	0
T24	0	134	0	0