Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1569895	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5576009

1

T24

150

T25

516

T1

3056

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3195486	1			T24	103		T25	612		T1	1815
values[0x0]	1969293	1			T24	57		T25	91		T1	1097
values[0x1]	1981125	1			T24	45		T25	113		T1	1063

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1247376	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5898528

1

T24

158

T25

587

T1

3259

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26959	1			T25	1		T1	19		T11	41
valid_sources[0x01]	23094	1			T25	1		T1	16		T11	25
valid_sources[0x02]	22573	1			T25	1		T1	17		T11	37
valid_sources[0x03]	144777	1			T25	4		T1	5		T11	39
valid_sources[0x04]	20179	1			T25	1		T1	17		T11	49
valid_sources[0x05]	23207	1			T25	5		T1	20		T11	35
valid_sources[0x06]	23649	1			T25	5		T1	12		T11	37
valid_sources[0x07]	26304	1			T25	1		T1	19		T11	49
valid_sources[0x08]	22232	1			T25	2		T1	14		T11	45
valid_sources[0x09]	20940	1			T25	5		T1	11		T11	41
valid_sources[0x0a]	23162	1			T25	5		T1	11		T11	34
valid_sources[0x0b]	20992	1			T25	4		T1	14		T11	39
valid_sources[0x0c]	26858	1			T25	5		T1	19		T11	46
valid_sources[0x0d]	22057	1			T25	4		T1	12		T11	28
valid_sources[0x0e]	25810	1			T25	8		T1	19		T11	42
valid_sources[0x0f]	22721	1			T25	3		T1	15		T11	34
valid_sources[0x10]	21898	1			T25	6		T1	10		T11	35
valid_sources[0x11]	25933	1			T25	2		T1	26		T11	40
valid_sources[0x12]	20658	1			T25	6		T1	9		T11	42
valid_sources[0x13]	23110	1			T25	3		T1	17		T11	31
valid_sources[0x14]	23057	1			T25	5		T1	15		T11	46
valid_sources[0x15]	24985	1			T24	22		T25	3		T1	10
valid_sources[0x16]	23278	1			T25	4		T1	13		T11	53
valid_sources[0x17]	22211	1			T25	1		T1	4		T11	31
valid_sources[0x18]	22314	1			T25	7		T1	15		T11	37
valid_sources[0x19]	21431	1			T25	4		T1	17		T11	37
valid_sources[0x1a]	21127	1			T25	3		T1	29		T11	29
valid_sources[0x1b]	25602	1			T25	2		T1	25		T11	43
valid_sources[0x1c]	21911	1			T25	5		T1	14		T11	30
valid_sources[0x1d]	28159	1			T25	4		T1	16		T11	43
valid_sources[0x1e]	21286	1			T24	21		T25	4		T1	14
valid_sources[0x1f]	22214	1			T25	1		T1	9		T11	44
valid_sources[0x20]	25274	1			T25	2		T1	14		T11	39
valid_sources[0x21]	23881	1			T25	7		T1	12		T11	45
valid_sources[0x22]	24082	1			T25	2		T1	9		T11	36
valid_sources[0x23]	23655	1			T25	4		T1	16		T11	27
valid_sources[0x24]	115002	1			T24	12		T25	4		T1	19
valid_sources[0x25]	24159	1			T25	1		T1	15		T11	30
valid_sources[0x26]	24589	1			T25	3		T1	16		T11	39
valid_sources[0x27]	24295	1			T25	1		T1	15		T11	34
valid_sources[0x28]	20649	1			T25	4		T1	13		T11	35
valid_sources[0x29]	24412	1			T25	7		T1	16		T11	29
valid_sources[0x2a]	21203	1			T25	2		T1	13		T11	41
valid_sources[0x2b]	25294	1			T25	4		T1	16		T11	39
valid_sources[0x2c]	21471	1			T25	3		T1	13		T11	46
valid_sources[0x2d]	22441	1			T25	4		T1	19		T11	54
valid_sources[0x2e]	21192	1			T25	2		T1	25		T11	37
valid_sources[0x2f]	57618	1			T25	6		T1	12		T11	38
valid_sources[0x30]	26721	1			T25	2		T1	12		T11	40
valid_sources[0x31]	26674	1			T25	4		T1	12		T11	45
valid_sources[0x32]	28947	1			T25	4		T1	12		T11	35
valid_sources[0x33]	22323	1			T25	4		T1	9		T11	38
valid_sources[0x34]	20017	1			T25	3		T1	21		T11	37
valid_sources[0x35]	21349	1			T25	4		T1	23		T11	36
valid_sources[0x36]	26733	1			T24	20		T25	4		T1	16
valid_sources[0x37]	21338	1			T25	3		T1	13		T11	34
valid_sources[0x38]	21870	1			T25	2		T1	12		T11	26
valid_sources[0x39]	24705	1			T25	3		T1	17		T11	46
valid_sources[0x3a]	21949	1			T25	2		T1	18		T11	21
valid_sources[0x3b]	24453	1			T24	4		T25	1		T1	8
valid_sources[0x3c]	28131	1			T25	3		T1	17		T11	36
valid_sources[0x3d]	26499	1			T24	6		T25	3		T1	16
valid_sources[0x3e]	20868	1			T25	2		T1	15		T11	42
valid_sources[0x3f]	21567	1			T25	6		T1	20		T11	51
valid_sources[0x40]	22221	1			T25	6		T1	19		T11	31
valid_sources[0x41]	27578	1			T1	11		T11	43		T13	2
valid_sources[0x42]	22265	1			T25	2		T1	18		T11	45
valid_sources[0x43]	25646	1			T25	8		T1	17		T11	34
valid_sources[0x44]	22078	1			T25	1		T1	15		T11	37
valid_sources[0x45]	25014	1			T25	5		T1	14		T11	52
valid_sources[0x46]	23582	1			T24	16		T25	2		T1	19
valid_sources[0x47]	21660	1			T25	2		T1	15		T11	33
valid_sources[0x48]	22220	1			T25	3		T1	13		T11	29
valid_sources[0x49]	23281	1			T25	9		T1	17		T11	41
valid_sources[0x4a]	23017	1			T25	3		T1	8		T11	35
valid_sources[0x4b]	23226	1			T25	1		T1	17		T11	43
valid_sources[0x4c]	23671	1			T25	3		T1	24		T11	32
valid_sources[0x4d]	21970	1			T25	1		T1	16		T11	35
valid_sources[0x4e]	23204	1			T25	2		T1	14		T11	46
valid_sources[0x4f]	28123	1			T25	2		T1	16		T11	35
valid_sources[0x50]	22623	1			T25	3		T1	14		T11	50
valid_sources[0x51]	31314	1			T25	3		T1	15		T11	32
valid_sources[0x52]	23804	1			T25	4		T1	15		T11	38
valid_sources[0x53]	23885	1			T25	3		T1	12		T11	52
valid_sources[0x54]	25175	1			T25	3		T1	24		T11	42
valid_sources[0x55]	115576	1			T25	3		T1	17		T11	36
valid_sources[0x56]	23203	1			T25	4		T1	18		T11	44
valid_sources[0x57]	24316	1			T25	4		T1	13		T11	41
valid_sources[0x58]	22796	1			T25	2		T1	12		T11	43
valid_sources[0x59]	19966	1			T25	2		T1	13		T11	34
valid_sources[0x5a]	21986	1			T25	3		T1	15		T11	36
valid_sources[0x5b]	23742	1			T25	1		T1	13		T11	33
valid_sources[0x5c]	24310	1			T25	3		T1	15		T11	40
valid_sources[0x5d]	22944	1			T25	1		T1	14		T11	45
valid_sources[0x5e]	22441	1			T25	4		T1	20		T11	41
valid_sources[0x5f]	21330	1			T25	6		T1	17		T11	37
valid_sources[0x60]	27281	1			T25	1		T1	9		T11	46
valid_sources[0x61]	26775	1			T25	3		T1	19		T11	37
valid_sources[0x62]	23192	1			T24	2		T25	2		T1	14
valid_sources[0x63]	30001	1			T1	16		T11	43		T13	1
valid_sources[0x64]	26262	1			T25	5		T1	20		T11	50
valid_sources[0x65]	23726	1			T1	10		T11	29		T12	2
valid_sources[0x66]	20403	1			T25	5		T1	21		T11	32
valid_sources[0x67]	20951	1			T25	1		T1	10		T11	22
valid_sources[0x68]	23122	1			T1	12		T11	45		T16	1
valid_sources[0x69]	73470	1			T25	2		T1	20		T11	26
valid_sources[0x6a]	22452	1			T25	4		T1	10		T11	34
valid_sources[0x6b]	26588	1			T25	7		T1	12		T11	28
valid_sources[0x6c]	21565	1			T25	3		T1	13		T11	29
valid_sources[0x6d]	20521	1			T25	7		T1	14		T11	53
valid_sources[0x6e]	20911	1			T25	4		T1	13		T11	40
valid_sources[0x6f]	25583	1			T25	1		T1	19		T11	48
valid_sources[0x70]	22753	1			T25	2		T1	14		T11	33
valid_sources[0x71]	20375	1			T25	5		T1	6		T11	31
valid_sources[0x72]	23370	1			T24	2		T25	1		T1	15
valid_sources[0x73]	23663	1			T25	3		T1	16		T11	38
valid_sources[0x74]	25237	1			T25	4		T1	20		T11	43
valid_sources[0x75]	23272	1			T25	1		T1	16		T11	38
valid_sources[0x76]	20846	1			T25	1		T1	17		T11	38
valid_sources[0x77]	22406	1			T25	3		T1	14		T11	39
valid_sources[0x78]	23231	1			T25	2		T1	18		T11	35
valid_sources[0x79]	25189	1			T25	3		T1	14		T11	35
valid_sources[0x7a]	21601	1			T25	6		T1	15		T11	33
valid_sources[0x7b]	21371	1			T25	4		T1	14		T11	44
valid_sources[0x7c]	25525	1			T25	2		T1	19		T11	44
valid_sources[0x7d]	23530	1			T1	25		T11	29		T13	3
valid_sources[0x7e]	22406	1			T25	1		T1	13		T11	32
valid_sources[0x7f]	110676	1			T25	4		T1	11		T11	42
valid_sources[0x80]	23425	1			T25	2		T1	16		T11	51

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1644567

1

T24

48

T25

312

T1

896

values[0x0]

all_enables

biggest_size

1967265

1

T24

57

T25

91

T1

1097

values[0x1]

all_enables

biggest_size

1964177

1

T24

45

T25

113

T1

1063