Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	55369153	0	0	0
ctrl_en_input_filter_rd_A	55369153	63571	0	0
intr_ctrl_en_falling_rd_A	55369153	64311	0	0
intr_ctrl_en_lvlhigh_rd_A	55369153	63538	0	0
intr_ctrl_en_lvllow_rd_A	55369153	65102	0	0
intr_ctrl_en_rising_rd_A	55369153	64418	0	0
intr_enable_rd_A	55369153	64519	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55369153	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55369153	63571	0	0
T1	38555	183	0	0
T2	0	7	0	0
T3	0	4761	0	0
T4	0	6	0	0
T5	0	69	0	0
T6	0	1	0	0
T7	0	196	0	0
T8	0	11	0	0
T9	0	103	0	0
T10	0	3413	0	0
T11	97046	0	0	0
T12	2673	0	0	0
T13	2153	0	0	0
T14	5931	0	0	0
T15	2555	0	0	0
T16	5255	0	0	0
T17	3760	0	0	0
T18	5787	0	0	0
T19	8791	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55369153	64311	0	0
T1	38555	134	0	0
T3	0	4874	0	0
T5	0	39	0	0
T6	0	6	0	0
T7	0	238	0	0
T8	0	1	0	0
T9	0	183	0	0
T10	0	3611	0	0
T11	97046	0	0	0
T12	2673	0	0	0
T13	2153	0	0	0
T14	5931	0	0	0
T15	2555	0	0	0
T16	5255	0	0	0
T17	3760	0	0	0
T18	5787	0	0	0
T19	8791	0	0	0
T20	0	8	0	0
T21	0	308	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55369153	63538	0	0
T1	38555	160	0	0
T2	0	3	0	0
T3	0	4794	0	0
T4	0	15	0	0
T5	0	81	0	0
T6	0	9	0	0
T7	0	168	0	0
T9	0	133	0	0
T10	0	3421	0	0
T11	97046	0	0	0
T12	2673	0	0	0
T13	2153	0	0	0
T14	5931	0	0	0
T15	2555	0	0	0
T16	5255	0	0	0
T17	3760	0	0	0
T18	5787	0	0	0
T19	8791	0	0	0
T20	0	9	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55369153	65102	0	0
T1	38555	169	0	0
T2	0	6	0	0
T3	0	4741	0	0
T5	0	53	0	0
T6	0	1	0	0
T7	0	196	0	0
T9	0	127	0	0
T10	0	3743	0	0
T11	97046	0	0	0
T12	2673	0	0	0
T13	2153	0	0	0
T14	5931	0	0	0
T15	2555	0	0	0
T16	5255	0	0	0
T17	3760	0	0	0
T18	5787	0	0	0
T19	8791	0	0	0
T21	0	311	0	0
T22	0	280	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55369153	64418	0	0
T1	38555	146	0	0
T3	0	4962	0	0
T5	0	54	0	0
T7	0	206	0	0
T9	0	112	0	0
T10	0	3491	0	0
T11	97046	0	0	0
T12	2673	0	0	0
T13	2153	0	0	0
T14	5931	0	0	0
T15	2555	0	0	0
T16	5255	0	0	0
T17	3760	0	0	0
T18	5787	0	0	0
T19	8791	0	0	0
T20	0	6	0	0
T21	0	266	0	0
T22	0	244	0	0
T23	0	8	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55369153	64519	0	0
T1	38555	196	0	0
T2	0	12	0	0
T3	0	4419	0	0
T5	0	65	0	0
T6	0	7	0	0
T7	0	220	0	0
T8	0	7	0	0
T9	0	109	0	0
T10	0	3621	0	0
T11	97046	0	0	0
T12	2673	0	0	0
T13	2153	0	0	0
T14	5931	0	0	0
T15	2555	0	0	0
T16	5255	0	0	0
T17	3760	0	0	0
T18	5787	0	0	0
T19	8791	0	0	0
T20	0	9	0	0