Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1091104	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3846144

1

T20

237

T21

126

T22

241

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2218141	1			T20	12		T21	93		T22	52
values[0x0]	1354122	1			T20	119		T21	44		T22	97
values[0x1]	1364985	1			T20	111		T21	40		T22	118

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	866725	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4070523

1

T20

240

T21

142

T22

246

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14839	1			T26	3		T27	1		T29	1
valid_sources[0x01]	14970	1			T20	2		T22	1		T26	4
valid_sources[0x02]	15210	1			T22	7		T26	3		T2	7
valid_sources[0x03]	86113	1			T26	1		T11	605		T12	5
valid_sources[0x04]	15685	1			T21	1		T26	3		T94	1
valid_sources[0x05]	15463	1			T21	1		T26	3		T27	2
valid_sources[0x06]	94433	1			T26	1		T12	4		T2	21
valid_sources[0x07]	53857	1			T21	3		T22	4		T26	4
valid_sources[0x08]	17928	1			T21	2		T26	1		T27	6
valid_sources[0x09]	16944	1			T21	2		T22	3		T26	5
valid_sources[0x0a]	16095	1			T21	3		T26	2		T28	1
valid_sources[0x0b]	14914	1			T21	1		T26	2		T95	5
valid_sources[0x0c]	15540	1			T21	2		T26	2		T27	2
valid_sources[0x0d]	16267	1			T26	2		T27	10		T12	2
valid_sources[0x0e]	14880	1			T22	4		T26	5		T27	6
valid_sources[0x0f]	20157	1			T26	3		T94	1		T96	2
valid_sources[0x10]	14406	1			T20	3		T26	3		T27	3
valid_sources[0x11]	16826	1			T26	2		T27	7		T95	4
valid_sources[0x12]	14616	1			T21	2		T22	3		T26	1
valid_sources[0x13]	15512	1			T26	3		T27	4		T12	2
valid_sources[0x14]	14912	1			T21	1		T26	1		T27	7
valid_sources[0x15]	15330	1			T26	3		T27	1		T29	1
valid_sources[0x16]	17320	1			T27	2		T2	4		T18	18
valid_sources[0x17]	14952	1			T22	3		T26	1		T12	3
valid_sources[0x18]	15389	1			T21	2		T26	4		T12	5
valid_sources[0x19]	15517	1			T26	2		T27	5		T28	1
valid_sources[0x1a]	15769	1			T26	2		T27	1		T29	2
valid_sources[0x1b]	37315	1			T22	6		T26	1		T12	1
valid_sources[0x1c]	14780	1			T21	1		T22	1		T26	4
valid_sources[0x1d]	15189	1			T21	1		T26	2		T27	6
valid_sources[0x1e]	15421	1			T26	4		T27	1		T2	3
valid_sources[0x1f]	17273	1			T21	2		T29	3		T12	6
valid_sources[0x20]	14836	1			T22	1		T26	4		T27	4
valid_sources[0x21]	17353	1			T21	1		T22	2		T26	3
valid_sources[0x22]	18102	1			T22	2		T26	4		T27	4
valid_sources[0x23]	15273	1			T22	2		T26	1		T27	1
valid_sources[0x24]	14539	1			T20	13		T22	4		T26	6
valid_sources[0x25]	107056	1			T26	8		T97	16		T12	5
valid_sources[0x26]	16459	1			T12	2		T2	4		T94	2
valid_sources[0x27]	17795	1			T22	2		T26	3		T27	1
valid_sources[0x28]	14690	1			T27	1		T29	5		T2	2
valid_sources[0x29]	17102	1			T26	1		T27	1		T29	1
valid_sources[0x2a]	15848	1			T21	5		T26	1		T27	4
valid_sources[0x2b]	15486	1			T21	1		T27	2		T12	3
valid_sources[0x2c]	16645	1			T26	2		T27	2		T29	5
valid_sources[0x2d]	15927	1			T21	2		T26	3		T2	5
valid_sources[0x2e]	15378	1			T20	9		T22	13		T26	1
valid_sources[0x2f]	15317	1			T26	1		T27	6		T12	1
valid_sources[0x30]	69485	1			T21	1		T22	1		T26	1
valid_sources[0x31]	16555	1			T22	4		T26	3		T27	7
valid_sources[0x32]	15078	1			T21	1		T12	5		T2	11
valid_sources[0x33]	19435	1			T21	1		T26	2		T97	9
valid_sources[0x34]	17858	1			T21	1		T22	3		T26	1
valid_sources[0x35]	14708	1			T26	2		T27	4		T29	2
valid_sources[0x36]	16053	1			T26	3		T27	1		T12	3
valid_sources[0x37]	15558	1			T26	4		T12	4		T2	1
valid_sources[0x38]	21852	1			T22	3		T26	3		T29	2
valid_sources[0x39]	14797	1			T26	4		T27	13		T12	1
valid_sources[0x3a]	15474	1			T22	1		T26	3		T29	5
valid_sources[0x3b]	14774	1			T21	1		T22	6		T26	2
valid_sources[0x3c]	15547	1			T21	2		T22	17		T26	4
valid_sources[0x3d]	14970	1			T26	3		T27	3		T29	1
valid_sources[0x3e]	15772	1			T21	2		T26	5		T95	4
valid_sources[0x3f]	20808	1			T21	3		T22	4		T26	5
valid_sources[0x40]	15124	1			T26	1		T27	2		T95	3
valid_sources[0x41]	15635	1			T21	3		T26	3		T27	8
valid_sources[0x42]	16183	1			T26	4		T27	4		T95	3
valid_sources[0x43]	16002	1			T21	3		T22	1		T26	5
valid_sources[0x44]	16221	1			T20	30		T27	2		T12	1
valid_sources[0x45]	16623	1			T22	2		T26	3		T95	6
valid_sources[0x46]	14947	1			T20	17		T21	1		T22	7
valid_sources[0x47]	15741	1			T26	1		T27	5		T95	2
valid_sources[0x48]	15719	1			T26	2		T27	6		T12	2
valid_sources[0x49]	16237	1			T22	1		T26	4		T27	9
valid_sources[0x4a]	14905	1			T21	4		T22	6		T26	1
valid_sources[0x4b]	15157	1			T22	6		T26	3		T27	3
valid_sources[0x4c]	15571	1			T21	1		T26	3		T27	3
valid_sources[0x4d]	15772	1			T26	3		T27	10		T12	2
valid_sources[0x4e]	16909	1			T21	1		T22	3		T26	4
valid_sources[0x4f]	15074	1			T26	1		T95	3		T12	3
valid_sources[0x50]	15345	1			T22	4		T26	1		T27	8
valid_sources[0x51]	14926	1			T21	1		T26	1		T27	3
valid_sources[0x52]	14965	1			T26	4		T27	1		T12	1
valid_sources[0x53]	15297	1			T22	6		T26	2		T27	3
valid_sources[0x54]	14875	1			T21	1		T26	4		T27	5
valid_sources[0x55]	16539	1			T26	3		T28	1		T12	4
valid_sources[0x56]	17065	1			T26	2		T29	3		T12	3
valid_sources[0x57]	20113	1			T21	1		T22	1		T26	4
valid_sources[0x58]	14566	1			T20	1		T21	1		T26	2
valid_sources[0x59]	17674	1			T21	1		T26	6		T29	1
valid_sources[0x5a]	14826	1			T26	2		T27	2		T12	1
valid_sources[0x5b]	16134	1			T26	4		T95	1		T2	32
valid_sources[0x5c]	16018	1			T26	1		T27	2		T29	2
valid_sources[0x5d]	17043	1			T21	1		T26	4		T27	3
valid_sources[0x5e]	19402	1			T26	3		T12	14		T2	4
valid_sources[0x5f]	19137	1			T22	2		T26	2		T27	2
valid_sources[0x60]	15729	1			T21	1		T26	6		T27	7
valid_sources[0x61]	15789	1			T20	3		T26	7		T27	3
valid_sources[0x62]	15594	1			T26	1		T27	6		T29	2
valid_sources[0x63]	16539	1			T21	3		T26	2		T27	11
valid_sources[0x64]	14886	1			T22	1		T26	5		T95	2
valid_sources[0x65]	16336	1			T21	1		T22	1		T26	5
valid_sources[0x66]	14582	1			T20	41		T26	4		T27	2
valid_sources[0x67]	14827	1			T24	314		T26	4		T12	1
valid_sources[0x68]	16777	1			T21	1		T22	5		T27	1
valid_sources[0x69]	107449	1			T20	3		T21	1		T26	1
valid_sources[0x6a]	18239	1			T21	3		T22	1		T12	2
valid_sources[0x6b]	14713	1			T26	6		T12	2		T2	1
valid_sources[0x6c]	15162	1			T21	1		T26	3		T95	2
valid_sources[0x6d]	15215	1			T21	2		T26	3		T27	4
valid_sources[0x6e]	16869	1			T26	2		T27	3		T12	1
valid_sources[0x6f]	14948	1			T26	1		T95	1		T12	1
valid_sources[0x70]	16990	1			T20	2		T21	2		T26	2
valid_sources[0x71]	16165	1			T20	2		T21	3		T26	3
valid_sources[0x72]	15638	1			T22	1		T26	2		T27	6
valid_sources[0x73]	16268	1			T20	16		T21	1		T26	2
valid_sources[0x74]	14921	1			T20	21		T21	1		T26	1
valid_sources[0x75]	18532	1			T26	3		T12	4		T2	29
valid_sources[0x76]	16715	1			T20	13		T26	2		T27	4
valid_sources[0x77]	19734	1			T21	1		T27	3		T29	6
valid_sources[0x78]	15772	1			T26	4		T29	3		T12	4
valid_sources[0x79]	17805	1			T21	1		T26	3		T27	2
valid_sources[0x7a]	20022	1			T21	1		T22	12		T12	4
valid_sources[0x7b]	15353	1			T26	5		T27	2		T12	3
valid_sources[0x7c]	16546	1			T21	3		T26	2		T2	3
valid_sources[0x7d]	16196	1			T27	8		T98	1		T99	1
valid_sources[0x7e]	18097	1			T27	2		T12	5		T18	12
valid_sources[0x7f]	18021	1			T21	1		T26	2		T27	6
valid_sources[0x80]	17054	1			T21	2		T26	2		T12	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1140961

1

T20

7

T21

42

T22

26

values[0x0]

all_enables

biggest_size

1352510

1

T20

119

T21

44

T22

97

values[0x1]

all_enables

biggest_size

1352673

1

T20

111

T21

40

T22

118