Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	39155666	0	0	0
ctrl_en_input_filter_rd_A	39155666	40320	0	0
intr_ctrl_en_falling_rd_A	39155666	39795	0	0
intr_ctrl_en_lvlhigh_rd_A	39155666	39584	0	0
intr_ctrl_en_lvllow_rd_A	39155666	40311	0	0
intr_ctrl_en_rising_rd_A	39155666	39346	0	0
intr_enable_rd_A	39155666	40019	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39155666	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39155666	40320	0	0
T1	8119	1	0	0
T2	13256	71	0	0
T3	0	279	0	0
T4	0	194	0	0
T5	0	28	0	0
T6	0	12	0	0
T7	0	377	0	0
T8	0	227	0	0
T9	0	490	0	0
T10	0	229	0	0
T11	2816	0	0	0
T12	4191	0	0	0
T13	997	0	0	0
T14	2854	0	0	0
T15	2364	0	0	0
T16	1171	0	0	0
T17	5461	0	0	0
T18	3752	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39155666	39795	0	0
T1	8119	6	0	0
T2	13256	91	0	0
T3	0	216	0	0
T4	0	278	0	0
T5	0	63	0	0
T6	0	3	0	0
T7	0	309	0	0
T8	0	200	0	0
T9	0	550	0	0
T10	0	219	0	0
T11	2816	0	0	0
T12	4191	0	0	0
T13	997	0	0	0
T14	2854	0	0	0
T15	2364	0	0	0
T16	1171	0	0	0
T17	5461	0	0	0
T18	3752	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39155666	39584	0	0
T1	8119	2	0	0
T2	13256	102	0	0
T3	0	241	0	0
T4	0	216	0	0
T5	0	15	0	0
T7	0	373	0	0
T8	0	221	0	0
T9	0	499	0	0
T10	0	210	0	0
T11	2816	0	0	0
T12	4191	0	0	0
T13	997	0	0	0
T14	2854	0	0	0
T15	2364	0	0	0
T16	1171	0	0	0
T17	5461	0	0	0
T18	3752	0	0	0
T19	0	136	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39155666	40311	0	0
T1	8119	1	0	0
T2	13256	73	0	0
T3	0	213	0	0
T4	0	244	0	0
T5	0	32	0	0
T6	0	1	0	0
T7	0	450	0	0
T8	0	203	0	0
T9	0	582	0	0
T10	0	303	0	0
T11	2816	0	0	0
T12	4191	0	0	0
T13	997	0	0	0
T14	2854	0	0	0
T15	2364	0	0	0
T16	1171	0	0	0
T17	5461	0	0	0
T18	3752	0	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39155666	39346	0	0
T1	8119	10	0	0
T2	13256	58	0	0
T3	0	325	0	0
T4	0	272	0	0
T5	0	37	0	0
T6	0	2	0	0
T7	0	303	0	0
T8	0	260	0	0
T9	0	507	0	0
T10	0	302	0	0
T11	2816	0	0	0
T12	4191	0	0	0
T13	997	0	0	0
T14	2854	0	0	0
T15	2364	0	0	0
T16	1171	0	0	0
T17	5461	0	0	0
T18	3752	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39155666	40019	0	0
T1	8119	7	0	0
T2	13256	109	0	0
T3	0	260	0	0
T4	0	265	0	0
T5	0	42	0	0
T6	0	10	0	0
T7	0	336	0	0
T8	0	135	0	0
T9	0	459	0	0
T10	0	275	0	0
T11	2816	0	0	0
T12	4191	0	0	0
T13	997	0	0	0
T14	2854	0	0	0
T15	2364	0	0	0
T16	1171	0	0	0
T17	5461	0	0	0
T18	3752	0	0	0