Unified Coverage Report :: Module :: prim_subreg

Module : prim_subreg

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_data_in	70.24	85.71	50.00			75.00
tb.dut.u_reg.u_intr_state	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_ctrl_en_rising	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_ctrl_en_falling	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_ctrl_en_lvlhigh	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_ctrl_en_lvllow	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ctrl_en_input_filter	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_data_in

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
70.24	85.71	50.00			75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
67.59	77.78	50.00			75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.75	100.00	99.01			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

---

Module Instance : tb.dut.u_reg.u_intr_state

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.75	100.00	99.01			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00

---

Module Instance : tb.dut.u_reg.u_intr_enable

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.75	100.00	99.01			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_intr_ctrl_en_rising

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.75	100.00	99.01			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_intr_ctrl_en_falling

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.75	100.00	99.01			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_intr_ctrl_en_lvlhigh

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.75	100.00	99.01			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_intr_ctrl_en_lvllow

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.75	100.00	99.01			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_ctrl_en_input_filter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.75	100.00	99.01			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Line Coverage for Module : prim_subreg

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T20 T21 T22 
57         1/1                q <= RESVAL;
           Tests:       T20 T21 T22 
58         1/1              end else if (wr_en) begin
           Tests:       T20 T21 T22 
59         1/1                q <= wr_data;
           Tests:       T20 T21 T22 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T20 T21 T22 
65         1/1            assign qe = wr_en;
           Tests:       T20 T21 T22 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T20 T21 T22 

---

Cond Coverage for Module : prim_subreg

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T20,T21,T22
1	Covered	T20,T21,T22

---

Branch Coverage for Module : prim_subreg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T20,T21,T22

56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T20,T21,T22
0	1	Covered	T20,T21,T22
0	0	Covered	T20,T21,T22

Line Coverage for Instance : tb.dut.u_reg.u_data_in

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T20 T21 T22 
57         1/1                q <= RESVAL;
           Tests:       T20 T21 T22 
58         1/1              end else if (wr_en) begin
           Tests:       T20 T21 T22 
59         1/1                q <= wr_data;
           Tests:       T20 T21 T22 
60                          end
                   ==>  MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T20 T21 T22 
65         0/1     ==>    assign qe = wr_en;
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T20 T21 T22 

---

Cond Coverage for Instance : tb.dut.u_reg.u_data_in

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Not Covered
1	Covered	T20,T21,T22

---

Branch Coverage for Instance : tb.dut.u_reg.u_data_in

	Line No.	Total	Covered	Percent
Branches		4	3	75.00
TERNARY	64	2	1	50.00
IF	56	2	2	100.00

64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Not Covered

56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==> (Excluded)
Exclude Annotation: [UNR]

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T20,T21,T22
0	1	Covered	T20,T21,T22
0	0	Excluded		[UNR]

Line Coverage for Instance : tb.dut.u_reg.u_intr_state

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T20 T21 T22 
57         1/1                q <= RESVAL;
           Tests:       T20 T21 T22 
58         1/1              end else if (wr_en) begin
           Tests:       T20 T21 T22 
59         1/1                q <= wr_data;
           Tests:       T20 T26 T27 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T20 T21 T22 
65         1/1            assign qe = wr_en;
           Tests:       T20 T21 T22 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T20 T21 T22 

---

Cond Coverage for Instance : tb.dut.u_reg.u_intr_state

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T20,T21,T22
1	Covered	T20,T26,T27

---

Branch Coverage for Instance : tb.dut.u_reg.u_intr_state

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T20,T26,T27
0	Covered	T20,T21,T22

56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T20,T21,T22
0	1	Covered	T20,T26,T27
0	0	Covered	T20,T21,T22

Line Coverage for Instance : tb.dut.u_reg.u_intr_enable

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T20 T21 T22 
57         1/1                q <= RESVAL;
           Tests:       T20 T21 T22 
58         1/1              end else if (wr_en) begin
           Tests:       T20 T21 T22 
59         1/1                q <= wr_data;
           Tests:       T20 T26 T27 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T20 T21 T22 
65         1/1            assign qe = wr_en;
           Tests:       T20 T26 T27 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T20 T21 T22 

---

Cond Coverage for Instance : tb.dut.u_reg.u_intr_enable

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T20,T21,T22
1	Covered	T20,T26,T27

---

Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T20,T26,T27
0	Covered	T20,T21,T22

56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T20,T21,T22
0	1	Covered	T20,T26,T27
0	0	Covered	T20,T21,T22

Line Coverage for Instance : tb.dut.u_reg.u_intr_ctrl_en_rising

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T20 T21 T22 
57         1/1                q <= RESVAL;
           Tests:       T20 T21 T22 
58         1/1              end else if (wr_en) begin
           Tests:       T20 T21 T22 
59         1/1                q <= wr_data;
           Tests:       T20 T26 T27 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T20 T21 T22 
65         1/1            assign qe = wr_en;
           Tests:       T20 T26 T27 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T20 T21 T22 

---

Cond Coverage for Instance : tb.dut.u_reg.u_intr_ctrl_en_rising

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T20,T21,T22
1	Covered	T20,T26,T27

---

Branch Coverage for Instance : tb.dut.u_reg.u_intr_ctrl_en_rising

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T20,T26,T27
0	Covered	T20,T21,T22

56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T20,T21,T22
0	1	Covered	T20,T26,T27
0	0	Covered	T20,T21,T22

Line Coverage for Instance : tb.dut.u_reg.u_intr_ctrl_en_falling

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T20 T21 T22 
57         1/1                q <= RESVAL;
           Tests:       T20 T21 T22 
58         1/1              end else if (wr_en) begin
           Tests:       T20 T21 T22 
59         1/1                q <= wr_data;
           Tests:       T20 T26 T27 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T20 T21 T22 
65         1/1            assign qe = wr_en;
           Tests:       T20 T26 T27 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T20 T21 T22 

---

Cond Coverage for Instance : tb.dut.u_reg.u_intr_ctrl_en_falling

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T20,T21,T22
1	Covered	T20,T26,T27

---

Branch Coverage for Instance : tb.dut.u_reg.u_intr_ctrl_en_falling

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T20,T26,T27
0	Covered	T20,T21,T22

56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T20,T21,T22
0	1	Covered	T20,T26,T27
0	0	Covered	T20,T21,T22

Line Coverage for Instance : tb.dut.u_reg.u_intr_ctrl_en_lvlhigh

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T20 T21 T22 
57         1/1                q <= RESVAL;
           Tests:       T20 T21 T22 
58         1/1              end else if (wr_en) begin
           Tests:       T20 T21 T22 
59         1/1                q <= wr_data;
           Tests:       T20 T26 T27 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T20 T21 T22 
65         1/1            assign qe = wr_en;
           Tests:       T20 T26 T27 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T20 T21 T22 

---

Cond Coverage for Instance : tb.dut.u_reg.u_intr_ctrl_en_lvlhigh

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T20,T21,T22
1	Covered	T20,T26,T27

---

Branch Coverage for Instance : tb.dut.u_reg.u_intr_ctrl_en_lvlhigh

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T20,T26,T27
0	Covered	T20,T21,T22

56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T20,T21,T22
0	1	Covered	T20,T26,T27
0	0	Covered	T20,T21,T22

Line Coverage for Instance : tb.dut.u_reg.u_intr_ctrl_en_lvllow

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T20 T21 T22 
57         1/1                q <= RESVAL;
           Tests:       T20 T21 T22 
58         1/1              end else if (wr_en) begin
           Tests:       T20 T21 T22 
59         1/1                q <= wr_data;
           Tests:       T20 T26 T27 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T20 T21 T22 
65         1/1            assign qe = wr_en;
           Tests:       T20 T26 T27 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T20 T21 T22 

---

Cond Coverage for Instance : tb.dut.u_reg.u_intr_ctrl_en_lvllow

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T20,T21,T22
1	Covered	T20,T26,T27

---

Branch Coverage for Instance : tb.dut.u_reg.u_intr_ctrl_en_lvllow

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T20,T26,T27
0	Covered	T20,T21,T22

56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T20,T21,T22
0	1	Covered	T20,T26,T27
0	0	Covered	T20,T21,T22

Line Coverage for Instance : tb.dut.u_reg.u_ctrl_en_input_filter

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T20 T21 T22 
57         1/1                q <= RESVAL;
           Tests:       T20 T21 T22 
58         1/1              end else if (wr_en) begin
           Tests:       T20 T21 T22 
59         1/1                q <= wr_data;
           Tests:       T20 T1 T11 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T20 T21 T22 
65         1/1            assign qe = wr_en;
           Tests:       T20 T1 T11 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T20 T21 T22 

---

Cond Coverage for Instance : tb.dut.u_reg.u_ctrl_en_input_filter

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T20,T21,T22
1	Covered	T20,T1,T11

---

Branch Coverage for Instance : tb.dut.u_reg.u_ctrl_en_input_filter

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T20,T1,T11
0	Covered	T20,T21,T22

56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T20,T21,T22
0	1	Covered	T20,T1,T11
0	0	Covered	T20,T21,T22