Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	1575004	1			T23	1		T24	1		T25	1
all_pins[1]	1575004	1			T23	1		T24	1		T25	1
all_pins[2]	1575004	1			T23	1		T24	1		T25	1
all_pins[3]	1575004	1			T23	1		T24	1		T25	1
all_pins[4]	1575004	1			T23	1		T24	1		T25	1
all_pins[5]	1575004	1			T23	1		T24	1		T25	1
all_pins[6]	1575004	1			T23	1		T24	1		T25	1
all_pins[7]	1575004	1			T23	1		T24	1		T25	1
all_pins[8]	1575004	1			T23	1		T24	1		T25	1
all_pins[9]	1575004	1			T23	1		T24	1		T25	1
all_pins[10]	1575004	1			T23	1		T24	1		T25	1
all_pins[11]	1575004	1			T23	1		T24	1		T25	1
all_pins[12]	1575004	1			T23	1		T24	1		T25	1
all_pins[13]	1575004	1			T23	1		T24	1		T25	1
all_pins[14]	1575004	1			T23	1		T24	1		T25	1
all_pins[15]	1575004	1			T23	1		T24	1		T25	1
all_pins[16]	1575004	1			T23	1		T24	1		T25	1
all_pins[17]	1575004	1			T23	1		T24	1		T25	1
all_pins[18]	1575004	1			T23	1		T24	1		T25	1
all_pins[19]	1575004	1			T23	1		T24	1		T25	1
all_pins[20]	1575004	1			T23	1		T24	1		T25	1
all_pins[21]	1575004	1			T23	1		T24	1		T25	1
all_pins[22]	1575004	1			T23	1		T24	1		T25	1
all_pins[23]	1575004	1			T23	1		T24	1		T25	1
all_pins[24]	1575004	1			T23	1		T24	1		T25	1
all_pins[25]	1575004	1			T23	1		T24	1		T25	1
all_pins[26]	1575004	1			T23	1		T24	1		T25	1
all_pins[27]	1575004	1			T23	1		T24	1		T25	1
all_pins[28]	1575004	1			T23	1		T24	1		T25	1
all_pins[29]	1575004	1			T23	1		T24	1		T25	1
all_pins[30]	1575004	1			T23	1		T24	1		T25	1
all_pins[31]	1575004	1			T23	1		T24	1		T25	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	31313842	1			T23	32		T24	32		T25	32
values[0x1]	19086286	1			T27	734		T29	1915		T30	719
transitions[0x0=>0x1]	11420627	1			T27	399		T29	881		T30	342
transitions[0x1=>0x0]	11420478	1			T27	399		T29	881		T30	342

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	980805	1			T23	1		T24	1		T25	1
all_pins[0]	values[0x1]	594199	1			T27	21		T29	29		T30	24
all_pins[0]	transitions[0x0=>0x1]	367385	1			T27	12		T29	15		T30	10
all_pins[0]	transitions[0x1=>0x0]	367569	1			T27	16		T29	20		T30	11
all_pins[1]	values[0x0]	979857	1			T23	1		T24	1		T25	1
all_pins[1]	values[0x1]	595147	1			T27	20		T29	40		T30	22
all_pins[1]	transitions[0x0=>0x1]	356169	1			T27	7		T29	36		T30	11
all_pins[1]	transitions[0x1=>0x0]	355221	1			T27	8		T29	25		T30	13
all_pins[2]	values[0x0]	976559	1			T23	1		T24	1		T25	1
all_pins[2]	values[0x1]	598445	1			T27	33		T29	47		T30	18
all_pins[2]	transitions[0x0=>0x1]	358315	1			T27	15		T29	13		T30	8
all_pins[2]	transitions[0x1=>0x0]	355017	1			T27	2		T29	6		T30	12
all_pins[3]	values[0x0]	979204	1			T23	1		T24	1		T25	1
all_pins[3]	values[0x1]	595800	1			T27	9		T29	74		T30	19
all_pins[3]	transitions[0x0=>0x1]	356409	1			T27	3		T29	42		T30	11
all_pins[3]	transitions[0x1=>0x0]	359054	1			T27	27		T29	15		T30	10
all_pins[4]	values[0x0]	979381	1			T23	1		T24	1		T25	1
all_pins[4]	values[0x1]	595623	1			T27	16		T29	65		T30	21
all_pins[4]	transitions[0x0=>0x1]	356452	1			T27	11		T29	15		T30	14
all_pins[4]	transitions[0x1=>0x0]	356629	1			T27	4		T29	24		T30	12
all_pins[5]	values[0x0]	979046	1			T23	1		T24	1		T25	1
all_pins[5]	values[0x1]	595958	1			T27	18		T29	35		T30	20
all_pins[5]	transitions[0x0=>0x1]	354693	1			T27	14		T29	20		T30	12
all_pins[5]	transitions[0x1=>0x0]	354358	1			T27	12		T29	50		T30	13
all_pins[6]	values[0x0]	977172	1			T23	1		T24	1		T25	1
all_pins[6]	values[0x1]	597832	1			T27	19		T29	65		T30	30
all_pins[6]	transitions[0x0=>0x1]	358884	1			T27	12		T29	61		T30	16
all_pins[6]	transitions[0x1=>0x0]	357010	1			T27	11		T29	31		T30	6
all_pins[7]	values[0x0]	976911	1			T23	1		T24	1		T25	1
all_pins[7]	values[0x1]	598093	1			T27	30		T29	50		T30	24
all_pins[7]	transitions[0x0=>0x1]	356783	1			T27	19		T29	14		T30	5
all_pins[7]	transitions[0x1=>0x0]	356522	1			T27	8		T29	29		T30	11
all_pins[8]	values[0x0]	977046	1			T23	1		T24	1		T25	1
all_pins[8]	values[0x1]	597958	1			T27	37		T29	49		T30	21
all_pins[8]	transitions[0x0=>0x1]	356354	1			T27	14		T29	18		T30	6
all_pins[8]	transitions[0x1=>0x0]	356489	1			T27	7		T29	19		T30	9
all_pins[9]	values[0x0]	977723	1			T23	1		T24	1		T25	1
all_pins[9]	values[0x1]	597281	1			T27	41		T29	93		T30	17
all_pins[9]	transitions[0x0=>0x1]	356492	1			T27	12		T29	51		T30	9
all_pins[9]	transitions[0x1=>0x0]	357169	1			T27	8		T29	7		T30	13
all_pins[10]	values[0x0]	979836	1			T23	1		T24	1		T25	1
all_pins[10]	values[0x1]	595168	1			T27	26		T29	69		T30	26
all_pins[10]	transitions[0x0=>0x1]	354965	1			T27	4		T29	17		T30	15
all_pins[10]	transitions[0x1=>0x0]	357078	1			T27	19		T29	41		T30	6
all_pins[11]	values[0x0]	979653	1			T23	1		T24	1		T25	1
all_pins[11]	values[0x1]	595351	1			T27	28		T29	28		T30	24
all_pins[11]	transitions[0x0=>0x1]	355509	1			T27	11		T29	18		T30	9
all_pins[11]	transitions[0x1=>0x0]	355326	1			T27	9		T29	59		T30	11
all_pins[12]	values[0x0]	979676	1			T23	1		T24	1		T25	1
all_pins[12]	values[0x1]	595328	1			T27	25		T29	20		T30	26
all_pins[12]	transitions[0x0=>0x1]	356673	1			T27	13		T29	14		T30	13
all_pins[12]	transitions[0x1=>0x0]	356696	1			T27	16		T29	22		T30	11
all_pins[13]	values[0x0]	978047	1			T23	1		T24	1		T25	1
all_pins[13]	values[0x1]	596957	1			T27	29		T29	76		T30	24
all_pins[13]	transitions[0x0=>0x1]	356830	1			T27	16		T29	67		T30	11
all_pins[13]	transitions[0x1=>0x0]	355201	1			T27	12		T29	11		T30	13
all_pins[14]	values[0x0]	980296	1			T23	1		T24	1		T25	1
all_pins[14]	values[0x1]	594708	1			T27	10		T29	86		T30	25
all_pins[14]	transitions[0x0=>0x1]	355745	1			T27	2		T29	17		T30	11
all_pins[14]	transitions[0x1=>0x0]	357994	1			T27	21		T29	7		T30	10
all_pins[15]	values[0x0]	978720	1			T23	1		T24	1		T25	1
all_pins[15]	values[0x1]	596284	1			T27	25		T29	67		T30	18
all_pins[15]	transitions[0x0=>0x1]	355717	1			T27	20		T29	24		T30	8
all_pins[15]	transitions[0x1=>0x0]	354141	1			T27	5		T29	43		T30	15
all_pins[16]	values[0x0]	978011	1			T23	1		T24	1		T25	1
all_pins[16]	values[0x1]	596993	1			T27	28		T29	67		T30	20
all_pins[16]	transitions[0x0=>0x1]	357360	1			T27	15		T29	29		T30	12
all_pins[16]	transitions[0x1=>0x0]	356651	1			T27	12		T29	29		T30	10
all_pins[17]	values[0x0]	979299	1			T23	1		T24	1		T25	1
all_pins[17]	values[0x1]	595705	1			T27	5		T29	66		T30	18
all_pins[17]	transitions[0x0=>0x1]	355449	1			T27	2		T29	22		T30	12
all_pins[17]	transitions[0x1=>0x0]	356737	1			T27	25		T29	23		T30	14
all_pins[18]	values[0x0]	977285	1			T23	1		T24	1		T25	1
all_pins[18]	values[0x1]	597719	1			T27	20		T29	67		T30	24
all_pins[18]	transitions[0x0=>0x1]	357493	1			T27	18		T29	28		T30	12
all_pins[18]	transitions[0x1=>0x0]	355479	1			T27	3		T29	27		T30	6
all_pins[19]	values[0x0]	977297	1			T23	1		T24	1		T25	1
all_pins[19]	values[0x1]	597707	1			T27	23		T29	84		T30	26
all_pins[19]	transitions[0x0=>0x1]	356425	1			T27	13		T29	36		T30	10
all_pins[19]	transitions[0x1=>0x0]	356437	1			T27	10		T29	19		T30	8
all_pins[20]	values[0x0]	976601	1			T23	1		T24	1		T25	1
all_pins[20]	values[0x1]	598403	1			T27	25		T29	58		T30	21
all_pins[20]	transitions[0x0=>0x1]	355860	1			T27	20		T29	12		T30	7
all_pins[20]	transitions[0x1=>0x0]	355164	1			T27	18		T29	38		T30	12
all_pins[21]	values[0x0]	978275	1			T23	1		T24	1		T25	1
all_pins[21]	values[0x1]	596729	1			T27	14		T29	42		T30	17
all_pins[21]	transitions[0x0=>0x1]	356821	1			T27	7		T29	28		T30	7
all_pins[21]	transitions[0x1=>0x0]	358495	1			T27	18		T29	44		T30	11
all_pins[22]	values[0x0]	979038	1			T23	1		T24	1		T25	1
all_pins[22]	values[0x1]	595966	1			T27	18		T29	77		T30	26
all_pins[22]	transitions[0x0=>0x1]	354922	1			T27	15		T29	45		T30	17
all_pins[22]	transitions[0x1=>0x0]	355685	1			T27	11		T29	10		T30	8
all_pins[23]	values[0x0]	980701	1			T23	1		T24	1		T25	1
all_pins[23]	values[0x1]	594303	1			T27	18		T29	60		T30	24
all_pins[23]	transitions[0x0=>0x1]	355772	1			T27	11		T29	20		T30	10
all_pins[23]	transitions[0x1=>0x0]	357435	1			T27	11		T29	37		T30	12
all_pins[24]	values[0x0]	980762	1			T23	1		T24	1		T25	1
all_pins[24]	values[0x1]	594242	1			T27	33		T29	77		T30	26
all_pins[24]	transitions[0x0=>0x1]	356587	1			T27	22		T29	32		T30	9
all_pins[24]	transitions[0x1=>0x0]	356648	1			T27	7		T29	15		T30	7
all_pins[25]	values[0x0]	980910	1			T23	1		T24	1		T25	1
all_pins[25]	values[0x1]	594094	1			T27	21		T29	83		T30	20
all_pins[25]	transitions[0x0=>0x1]	356462	1			T27	5		T29	24		T30	10
all_pins[25]	transitions[0x1=>0x0]	356610	1			T27	17		T29	18		T30	16
all_pins[26]	values[0x0]	975204	1			T23	1		T24	1		T25	1
all_pins[26]	values[0x1]	599800	1			T27	24		T29	52		T30	17
all_pins[26]	transitions[0x0=>0x1]	361159	1			T27	15		T29	15		T30	10
all_pins[26]	transitions[0x1=>0x0]	355453	1			T27	12		T29	46		T30	13
all_pins[27]	values[0x0]	976861	1			T23	1		T24	1		T25	1
all_pins[27]	values[0x1]	598143	1			T27	22		T29	45		T30	23
all_pins[27]	transitions[0x0=>0x1]	356798	1			T27	17		T29	43		T30	13
all_pins[27]	transitions[0x1=>0x0]	358455	1			T27	19		T29	50		T30	7
all_pins[28]	values[0x0]	976499	1			T23	1		T24	1		T25	1
all_pins[28]	values[0x1]	598505	1			T27	30		T29	56		T30	20
all_pins[28]	transitions[0x0=>0x1]	357145	1			T27	14		T29	39		T30	10
all_pins[28]	transitions[0x1=>0x0]	356783	1			T27	6		T29	28		T30	13
all_pins[29]	values[0x0]	978286	1			T23	1		T24	1		T25	1
all_pins[29]	values[0x1]	596718	1			T27	27		T29	71		T30	30
all_pins[29]	transitions[0x0=>0x1]	356613	1			T27	12		T29	38		T30	18
all_pins[29]	transitions[0x1=>0x0]	358400	1			T27	15		T29	23		T30	8
all_pins[30]	values[0x0]	978409	1			T23	1		T24	1		T25	1
all_pins[30]	values[0x1]	596595	1			T27	14		T29	83		T30	23
all_pins[30]	transitions[0x0=>0x1]	356727	1			T27	10		T29	25		T30	7
all_pins[30]	transitions[0x1=>0x0]	356850	1			T27	23		T29	13		T30	14
all_pins[31]	values[0x0]	980472	1			T23	1		T24	1		T25	1
all_pins[31]	values[0x1]	594532	1			T27	25		T29	34		T30	25
all_pins[31]	transitions[0x0=>0x1]	355659	1			T27	18		T29	3		T30	9
all_pins[31]	transitions[0x1=>0x0]	357722	1			T27	7		T29	52		T30	7