Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	6311033	1			T23	442		T24	202		T25	231
all_values[1]	6311033	1			T23	442		T24	202		T25	231
all_values[2]	6311033	1			T23	442		T24	202		T25	231
all_values[3]	6311033	1			T23	442		T24	202		T25	231
all_values[4]	6311033	1			T23	442		T24	202		T25	231
all_values[5]	6311033	1			T23	442		T24	202		T25	231
all_values[6]	6311033	1			T23	442		T24	202		T25	231
all_values[7]	6311033	1			T23	442		T24	202		T25	231
all_values[8]	6311033	1			T23	442		T24	202		T25	231
all_values[9]	6311033	1			T23	442		T24	202		T25	231
all_values[10]	6311033	1			T23	442		T24	202		T25	231
all_values[11]	6311033	1			T23	442		T24	202		T25	231
all_values[12]	6311033	1			T23	442		T24	202		T25	231
all_values[13]	6311033	1			T23	442		T24	202		T25	231
all_values[14]	6311033	1			T23	442		T24	202		T25	231
all_values[15]	6311033	1			T23	442		T24	202		T25	231
all_values[16]	6311033	1			T23	442		T24	202		T25	231
all_values[17]	6311033	1			T23	442		T24	202		T25	231
all_values[18]	6311033	1			T23	442		T24	202		T25	231
all_values[19]	6311033	1			T23	442		T24	202		T25	231
all_values[20]	6311033	1			T23	442		T24	202		T25	231
all_values[21]	6311033	1			T23	442		T24	202		T25	231
all_values[22]	6311033	1			T23	442		T24	202		T25	231
all_values[23]	6311033	1			T23	442		T24	202		T25	231
all_values[24]	6311033	1			T23	442		T24	202		T25	231
all_values[25]	6311033	1			T23	442		T24	202		T25	231
all_values[26]	6311033	1			T23	442		T24	202		T25	231
all_values[27]	6311033	1			T23	442		T24	202		T25	231
all_values[28]	6311033	1			T23	442		T24	202		T25	231
all_values[29]	6311033	1			T23	442		T24	202		T25	231
all_values[30]	6311033	1			T23	442		T24	202		T25	231
all_values[31]	6311033	1			T23	442		T24	202		T25	231

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

133217388

1

T23

14144

T24

6464

T25

7392

auto[1]

68735668

1

T27

1586

T29

7188

T31

185

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

77884382

1

T23

14144

T24

6464

T25

7392

auto[1]

124068674

1

T27

2816

T29

12632

T31

328

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

200046726

1

T23

14144

T24

6464

T25

7392

auto[1]

1906330

1

T31

48

T33

2755

T43

140

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2218733	1			T23	442		T24	202		T25	231
all_values[0]	auto[0]	auto[0]	auto[1]	1915983	1			T27	64		T29	264		T31	11
all_values[0]	auto[0]	auto[1]	auto[0]	220170	1			T29	6		T31	2		T33	211
all_values[0]	auto[0]	auto[1]	auto[1]	1896498	1			T27	32		T29	104		T31	3
all_values[0]	auto[1]	auto[0]	auto[1]	29636	1			T31	1		T33	39		T43	2
all_values[0]	auto[1]	auto[1]	auto[1]	30013	1			T33	44		T43	2		T108	33
all_values[1]	auto[0]	auto[0]	auto[0]	2221791	1			T23	442		T24	202		T25	231
all_values[1]	auto[0]	auto[0]	auto[1]	1920071	1			T27	59		T29	250		T31	10
all_values[1]	auto[0]	auto[1]	auto[0]	214253	1			T27	2		T29	14		T31	5
all_values[1]	auto[0]	auto[1]	auto[1]	1895596	1			T27	32		T29	137		T33	770
all_values[1]	auto[1]	auto[0]	auto[1]	29872	1			T33	57		T43	1		T108	31
all_values[1]	auto[1]	auto[1]	auto[1]	29450	1			T33	26		T43	3		T108	36
all_values[2]	auto[0]	auto[0]	auto[0]	2223319	1			T23	442		T24	202		T25	231
all_values[2]	auto[0]	auto[0]	auto[1]	1915288	1			T27	39		T29	211		T31	2
all_values[2]	auto[0]	auto[1]	auto[0]	213694	1			T27	5		T29	43		T31	4
all_values[2]	auto[0]	auto[1]	auto[1]	1899270	1			T27	58		T29	174		T31	7
all_values[2]	auto[1]	auto[0]	auto[1]	30139	1			T31	1		T33	40		T43	3
all_values[2]	auto[1]	auto[1]	auto[1]	29323	1			T31	1		T33	43		T43	2
all_values[3]	auto[0]	auto[0]	auto[0]	2220366	1			T23	442		T24	202		T25	231
all_values[3]	auto[0]	auto[0]	auto[1]	1915347	1			T27	59		T29	128		T31	10
all_values[3]	auto[0]	auto[1]	auto[0]	212606	1			T27	3		T29	28		T33	154
all_values[3]	auto[0]	auto[1]	auto[1]	1903277	1			T27	22		T29	260		T31	2
all_values[3]	auto[1]	auto[0]	auto[1]	29944	1			T33	46		T43	3		T108	30
all_values[3]	auto[1]	auto[1]	auto[1]	29493	1			T31	1		T33	53		T43	1
all_values[4]	auto[0]	auto[0]	auto[0]	2220290	1			T23	442		T24	202		T25	231
all_values[4]	auto[0]	auto[0]	auto[1]	1918716	1			T27	40		T29	154		T31	7
all_values[4]	auto[0]	auto[1]	auto[0]	214230	1			T27	27		T29	46		T33	111
all_values[4]	auto[0]	auto[1]	auto[1]	1898317	1			T27	35		T29	216		T33	897
all_values[4]	auto[1]	auto[0]	auto[1]	29909	1			T31	1		T33	46		T43	2
all_values[4]	auto[1]	auto[1]	auto[1]	29571	1			T33	32		T43	2		T108	42
all_values[5]	auto[0]	auto[0]	auto[0]	2221010	1			T23	442		T24	202		T25	231
all_values[5]	auto[0]	auto[0]	auto[1]	1906981	1			T27	54		T29	321		T31	11
all_values[5]	auto[0]	auto[1]	auto[0]	211188	1			T27	4		T29	1		T31	5
all_values[5]	auto[0]	auto[1]	auto[1]	1912178	1			T27	41		T29	106		T33	955
all_values[5]	auto[1]	auto[0]	auto[1]	30070	1			T31	1		T33	36		T43	3
all_values[5]	auto[1]	auto[1]	auto[1]	29606	1			T33	36		T43	3		T108	26
all_values[6]	auto[0]	auto[0]	auto[0]	2219223	1			T23	442		T24	202		T25	231
all_values[6]	auto[0]	auto[0]	auto[1]	1909591	1			T27	41		T29	152		T31	8
all_values[6]	auto[0]	auto[1]	auto[0]	215236	1			T27	10		T29	29		T33	115
all_values[6]	auto[0]	auto[1]	auto[1]	1907390	1			T27	33		T29	235		T31	2
all_values[6]	auto[1]	auto[0]	auto[1]	29838	1			T31	1		T33	39		T43	7
all_values[6]	auto[1]	auto[1]	auto[1]	29755	1			T31	1		T33	39		T43	1
all_values[7]	auto[0]	auto[0]	auto[0]	2216990	1			T23	442		T24	202		T25	231
all_values[7]	auto[0]	auto[0]	auto[1]	1897835	1			T27	38		T29	149		T31	6
all_values[7]	auto[0]	auto[1]	auto[0]	213880	1			T29	25		T31	5		T33	162
all_values[7]	auto[0]	auto[1]	auto[1]	1922596	1			T27	48		T29	206		T33	886
all_values[7]	auto[1]	auto[0]	auto[1]	30136	1			T33	47		T43	1		T108	31
all_values[7]	auto[1]	auto[1]	auto[1]	29596	1			T33	42		T43	3		T108	43
all_values[8]	auto[0]	auto[0]	auto[0]	2217679	1			T23	442		T24	202		T25	231
all_values[8]	auto[0]	auto[0]	auto[1]	1915815	1			T27	22		T29	260		T31	7
all_values[8]	auto[0]	auto[1]	auto[0]	213105	1			T27	5		T29	9		T33	193
all_values[8]	auto[0]	auto[1]	auto[1]	1905169	1			T27	66		T29	148		T31	3
all_values[8]	auto[1]	auto[0]	auto[1]	29990	1			T33	48		T43	3		T108	33
all_values[8]	auto[1]	auto[1]	auto[1]	29275	1			T33	34		T43	1		T108	48
all_values[9]	auto[0]	auto[0]	auto[0]	2218859	1			T23	442		T24	202		T25	231
all_values[9]	auto[0]	auto[0]	auto[1]	1898795	1			T27	29		T29	109		T33	1158
all_values[9]	auto[0]	auto[1]	auto[0]	214054	1			T27	2		T29	5		T31	1
all_values[9]	auto[0]	auto[1]	auto[1]	1919511	1			T27	67		T29	305		T31	6
all_values[9]	auto[1]	auto[0]	auto[1]	30085	1			T31	1		T33	50		T43	3
all_values[9]	auto[1]	auto[1]	auto[1]	29729	1			T33	33		T43	2		T108	34
all_values[10]	auto[0]	auto[0]	auto[0]	2217733	1			T23	442		T24	202		T25	231
all_values[10]	auto[0]	auto[0]	auto[1]	1919965	1			T27	48		T29	161		T31	10
all_values[10]	auto[0]	auto[1]	auto[0]	216059	1			T27	4		T29	6		T31	3
all_values[10]	auto[0]	auto[1]	auto[1]	1897494	1			T27	45		T29	219		T31	1
all_values[10]	auto[1]	auto[0]	auto[1]	30467	1			T31	2		T33	36		T43	2
all_values[10]	auto[1]	auto[1]	auto[1]	29315	1			T31	1		T33	50		T43	1
all_values[11]	auto[0]	auto[0]	auto[0]	2218491	1			T23	442		T24	202		T25	231
all_values[11]	auto[0]	auto[0]	auto[1]	1911889	1			T27	46		T29	241		T31	2
all_values[11]	auto[0]	auto[1]	auto[0]	213546	1			T29	12		T33	180		T34	12
all_values[11]	auto[0]	auto[1]	auto[1]	1907710	1			T27	41		T29	113		T31	7
all_values[11]	auto[1]	auto[0]	auto[1]	30380	1			T31	1		T33	49		T43	2
all_values[11]	auto[1]	auto[1]	auto[1]	29017	1			T33	37		T43	2		T108	35
all_values[12]	auto[0]	auto[0]	auto[0]	2221067	1			T23	442		T24	202		T25	231
all_values[12]	auto[0]	auto[0]	auto[1]	1905232	1			T27	43		T29	338		T31	8
all_values[12]	auto[0]	auto[1]	auto[0]	214397	1			T27	8		T29	9		T31	2
all_values[12]	auto[0]	auto[1]	auto[1]	1910866	1			T27	45		T29	61		T31	6
all_values[12]	auto[1]	auto[0]	auto[1]	29846	1			T33	53		T43	1		T108	27
all_values[12]	auto[1]	auto[1]	auto[1]	29625	1			T31	1		T33	40		T43	2
all_values[13]	auto[0]	auto[0]	auto[0]	2218151	1			T23	442		T24	202		T25	231
all_values[13]	auto[0]	auto[0]	auto[1]	1906727	1			T27	30		T29	125		T31	4
all_values[13]	auto[0]	auto[1]	auto[0]	217693	1			T27	4		T29	11		T31	3
all_values[13]	auto[0]	auto[1]	auto[1]	1908734	1			T27	64		T29	282		T31	1
all_values[13]	auto[1]	auto[0]	auto[1]	30129	1			T31	1		T33	54		T43	3
all_values[13]	auto[1]	auto[1]	auto[1]	29599	1			T31	1		T33	44		T43	3
all_values[14]	auto[0]	auto[0]	auto[0]	2219721	1			T23	442		T24	202		T25	231
all_values[14]	auto[0]	auto[0]	auto[1]	1928067	1			T27	78		T29	142		T33	895
all_values[14]	auto[0]	auto[1]	auto[0]	215336	1			T29	1		T31	4		T33	127
all_values[14]	auto[0]	auto[1]	auto[1]	1888373	1			T27	20		T29	283		T33	1048
all_values[14]	auto[1]	auto[0]	auto[1]	29957	1			T33	53		T108	42		T109	2
all_values[14]	auto[1]	auto[1]	auto[1]	29579	1			T33	37		T43	5		T108	32
all_values[15]	auto[0]	auto[0]	auto[0]	2221300	1			T23	442		T24	202		T25	231
all_values[15]	auto[0]	auto[0]	auto[1]	1917067	1			T27	42		T29	201		T31	6
all_values[15]	auto[0]	auto[1]	auto[0]	213830	1			T27	5		T29	8		T33	187
all_values[15]	auto[0]	auto[1]	auto[1]	1899174	1			T27	52		T29	212		T33	814
all_values[15]	auto[1]	auto[0]	auto[1]	30098	1			T33	47		T43	1		T108	23
all_values[15]	auto[1]	auto[1]	auto[1]	29564	1			T33	45		T43	3		T108	37
all_values[16]	auto[0]	auto[0]	auto[0]	2217424	1			T23	442		T24	202		T25	231
all_values[16]	auto[0]	auto[0]	auto[1]	1910698	1			T27	36		T29	151		T31	11
all_values[16]	auto[0]	auto[1]	auto[0]	213542	1			T27	5		T29	19		T33	134
all_values[16]	auto[0]	auto[1]	auto[1]	1909577	1			T27	53		T29	249		T33	965
all_values[16]	auto[1]	auto[0]	auto[1]	29983	1			T31	3		T33	38		T43	3
all_values[16]	auto[1]	auto[1]	auto[1]	29809	1			T33	45		T43	1		T108	29
all_values[17]	auto[0]	auto[0]	auto[0]	2222005	1			T23	442		T24	202		T25	231
all_values[17]	auto[0]	auto[0]	auto[1]	1926537	1			T27	76		T29	110		T31	9
all_values[17]	auto[0]	auto[1]	auto[0]	216802	1			T27	3		T29	30		T33	118
all_values[17]	auto[0]	auto[1]	auto[1]	1886265	1			T27	12		T29	264		T31	3
all_values[17]	auto[1]	auto[0]	auto[1]	29877	1			T31	1		T33	40		T43	4
all_values[17]	auto[1]	auto[1]	auto[1]	29547	1			T33	46		T43	3		T108	42
all_values[18]	auto[0]	auto[0]	auto[0]	2219236	1			T23	442		T24	202		T25	231
all_values[18]	auto[0]	auto[0]	auto[1]	1906922	1			T27	41		T29	162		T31	9
all_values[18]	auto[0]	auto[1]	auto[0]	217255	1			T27	11		T29	15		T31	2
all_values[18]	auto[0]	auto[1]	auto[1]	1907877	1			T27	37		T29	238		T31	2
all_values[18]	auto[1]	auto[0]	auto[1]	30106	1			T31	1		T33	53		T43	4
all_values[18]	auto[1]	auto[1]	auto[1]	29637	1			T31	1		T33	30		T43	1
all_values[19]	auto[0]	auto[0]	auto[0]	2219222	1			T23	442		T24	202		T25	231
all_values[19]	auto[0]	auto[0]	auto[1]	1908439	1			T27	48		T29	135		T31	11
all_values[19]	auto[0]	auto[1]	auto[0]	214754	1			T27	5		T29	10		T31	4
all_values[19]	auto[0]	auto[1]	auto[1]	1909145	1			T27	37		T29	277		T33	913
all_values[19]	auto[1]	auto[0]	auto[1]	29548	1			T31	1		T33	38		T43	2
all_values[19]	auto[1]	auto[1]	auto[1]	29925	1			T31	1		T33	47		T108	42
all_values[20]	auto[0]	auto[0]	auto[0]	2218188	1			T23	442		T24	202		T25	231
all_values[20]	auto[0]	auto[0]	auto[1]	1915066	1			T27	41		T29	217		T31	1
all_values[20]	auto[0]	auto[1]	auto[0]	216468	1			T27	4		T29	8		T31	7
all_values[20]	auto[0]	auto[1]	auto[1]	1901958	1			T27	51		T29	184		T33	868
all_values[20]	auto[1]	auto[0]	auto[1]	30012	1			T33	49		T43	3		T108	37
all_values[20]	auto[1]	auto[1]	auto[1]	29341	1			T31	1		T33	35		T43	3
all_values[21]	auto[0]	auto[0]	auto[0]	2221824	1			T23	442		T24	202		T25	231
all_values[21]	auto[0]	auto[0]	auto[1]	1903902	1			T27	30		T29	244		T31	7
all_values[21]	auto[0]	auto[1]	auto[0]	213444	1			T27	30		T29	17		T31	3
all_values[21]	auto[0]	auto[1]	auto[1]	1912230	1			T27	41		T29	158		T31	1
all_values[21]	auto[1]	auto[0]	auto[1]	29693	1			T31	2		T33	48		T43	3
all_values[21]	auto[1]	auto[1]	auto[1]	29940	1			T31	1		T33	47		T43	2
all_values[22]	auto[0]	auto[0]	auto[0]	2218971	1			T23	442		T24	202		T25	231
all_values[22]	auto[0]	auto[0]	auto[1]	1918318	1			T27	49		T29	113		T31	7
all_values[22]	auto[0]	auto[1]	auto[0]	213917	1			T27	14		T29	17		T31	2
all_values[22]	auto[0]	auto[1]	auto[1]	1899904	1			T27	31		T29	275		T31	5
all_values[22]	auto[1]	auto[0]	auto[1]	30484	1			T33	42		T43	2		T108	29
all_values[22]	auto[1]	auto[1]	auto[1]	29439	1			T31	1		T33	43		T43	1
all_values[23]	auto[0]	auto[0]	auto[0]	2217031	1			T23	442		T24	202		T25	231
all_values[23]	auto[0]	auto[0]	auto[1]	1913331	1			T27	44		T29	194		T31	4
all_values[23]	auto[0]	auto[1]	auto[0]	215245	1			T27	19		T29	12		T31	6
all_values[23]	auto[0]	auto[1]	auto[1]	1905883	1			T27	34		T29	208		T33	1088
all_values[23]	auto[1]	auto[0]	auto[1]	30145	1			T33	33		T43	2		T108	25
all_values[23]	auto[1]	auto[1]	auto[1]	29398	1			T31	2		T33	52		T43	3
all_values[24]	auto[0]	auto[0]	auto[0]	2219235	1			T23	442		T24	202		T25	231
all_values[24]	auto[0]	auto[0]	auto[1]	1920503	1			T27	31		T29	152		T33	878
all_values[24]	auto[0]	auto[1]	auto[0]	214917	1			T29	6		T31	2		T33	137
all_values[24]	auto[0]	auto[1]	auto[1]	1896736	1			T27	62		T29	241		T31	4
all_values[24]	auto[1]	auto[0]	auto[1]	29961	1			T31	1		T33	46		T43	4
all_values[24]	auto[1]	auto[1]	auto[1]	29681	1			T31	1		T33	39		T108	34
all_values[25]	auto[0]	auto[0]	auto[0]	2214335	1			T23	442		T24	202		T25	231
all_values[25]	auto[0]	auto[0]	auto[1]	1937327	1			T27	46		T29	94		T31	3
all_values[25]	auto[0]	auto[1]	auto[0]	215001	1			T27	1		T29	56		T31	2
all_values[25]	auto[0]	auto[1]	auto[1]	1884893	1			T27	44		T29	279		T31	8
all_values[25]	auto[1]	auto[0]	auto[1]	29568	1			T33	34		T43	1		T108	30
all_values[25]	auto[1]	auto[1]	auto[1]	29909	1			T31	2		T33	53		T43	3
all_values[26]	auto[0]	auto[0]	auto[0]	2219204	1			T23	442		T24	202		T25	231
all_values[26]	auto[0]	auto[0]	auto[1]	1903669	1			T27	48		T29	182		T31	6
all_values[26]	auto[0]	auto[1]	auto[0]	214506	1			T27	12		T29	22		T33	132
all_values[26]	auto[0]	auto[1]	auto[1]	1914212	1			T27	42		T29	213		T31	4
all_values[26]	auto[1]	auto[0]	auto[1]	29804	1			T31	2		T33	40		T43	4
all_values[26]	auto[1]	auto[1]	auto[1]	29638	1			T33	52		T43	2		T108	30
all_values[27]	auto[0]	auto[0]	auto[0]	2218869	1			T23	442		T24	202		T25	231
all_values[27]	auto[0]	auto[0]	auto[1]	1907866	1			T27	65		T29	248		T33	864
all_values[27]	auto[0]	auto[1]	auto[0]	216867	1			T29	3		T31	3		T33	214
all_values[27]	auto[0]	auto[1]	auto[1]	1907906	1			T27	33		T29	172		T31	5
all_values[27]	auto[1]	auto[0]	auto[1]	29960	1			T31	2		T33	43		T43	1
all_values[27]	auto[1]	auto[1]	auto[1]	29565	1			T31	1		T33	43		T43	1
all_values[28]	auto[0]	auto[0]	auto[0]	2217330	1			T23	442		T24	202		T25	231
all_values[28]	auto[0]	auto[0]	auto[1]	1902953	1			T27	31		T29	249		T31	7
all_values[28]	auto[0]	auto[1]	auto[0]	215928	1			T27	6		T31	5		T33	135
all_values[28]	auto[0]	auto[1]	auto[1]	1915170	1			T27	57		T29	163		T31	4
all_values[28]	auto[1]	auto[0]	auto[1]	30051	1			T31	1		T33	42		T43	2
all_values[28]	auto[1]	auto[1]	auto[1]	29601	1			T33	44		T43	2		T108	36
all_values[29]	auto[0]	auto[0]	auto[0]	2216428	1			T23	442		T24	202		T25	231
all_values[29]	auto[0]	auto[0]	auto[1]	1931527	1			T27	37		T29	120		T31	4
all_values[29]	auto[0]	auto[1]	auto[0]	213476	1			T27	14		T29	10		T31	6
all_values[29]	auto[0]	auto[1]	auto[1]	1890004	1			T27	53		T29	277		T33	860
all_values[29]	auto[1]	auto[0]	auto[1]	30101	1			T33	46		T43	1		T108	29
all_values[29]	auto[1]	auto[1]	auto[1]	29497	1			T31	2		T33	36		T43	2
all_values[30]	auto[0]	auto[0]	auto[0]	2219995	1			T23	442		T24	202		T25	231
all_values[30]	auto[0]	auto[0]	auto[1]	1916754	1			T27	51		T29	98		T31	6
all_values[30]	auto[0]	auto[1]	auto[0]	213956	1			T27	12		T29	12		T31	2
all_values[30]	auto[0]	auto[1]	auto[1]	1900921	1			T27	30		T29	288		T31	6
all_values[30]	auto[1]	auto[0]	auto[1]	29877	1			T31	2		T33	50		T43	2
all_values[30]	auto[1]	auto[1]	auto[1]	29530	1			T31	1		T33	37		T43	1
all_values[31]	auto[0]	auto[0]	auto[0]	2218495	1			T23	442		T24	202		T25	231
all_values[31]	auto[0]	auto[0]	auto[1]	1918020	1			T27	45		T29	266		T31	7
all_values[31]	auto[0]	auto[1]	auto[0]	212512	1			T27	6		T29	7		T33	168
all_values[31]	auto[0]	auto[1]	auto[1]	1902309	1			T27	47		T29	144		T31	6
all_values[31]	auto[1]	auto[0]	auto[1]	30006	1			T31	1		T33	36		T43	2
all_values[31]	auto[1]	auto[1]	auto[1]	29691	1			T31	1		T33	53		T43	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal