Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[1]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[2]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[3]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[4]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[5]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[6]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[7]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[8]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[9]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[10]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[11]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[12]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[13]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[14]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[15]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[16]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[17]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[18]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[19]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[20]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[21]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[22]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[23]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[24]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[25]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[26]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[27]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[28]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[29]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[30]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[31]	6242400	1			T23	774		T24	334		T25	450

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

108296606

1

T23

7142

T24

7623

T25

11303

auto[1]

91460194

1

T23

17626

T24

3065

T25

3097

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

165693816

1

T23

14182

T24

6491

T25

10503

auto[1]

34062984

1

T23

10586

T24

4197

T25

3897

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

156018761

1

T23

14296

T24

6644

T25

6999

auto[1]

43738039

1

T23

10472

T24

4044

T25

7401

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	2306323	1			T23	46		T24	74		T25	199
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	2032153	1			T23	243		T24	37		T25	13
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	537335	1			T23	217		T24	72		T25	49
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	544819	1			T24	87		T25	103		T26	153
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	289030	1			T23	132		T25	23		T26	14
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	532740	1			T23	136		T24	64		T25	63
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	2300730	1			T23	54		T24	106		T25	138
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	2040360	1			T23	209		T24	31		T25	14
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	534183	1			T23	176		T24	66		T25	30
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	547669	1			T24	73		T25	155		T26	165
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	289015	1			T23	142		T25	30		T26	19
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	530443	1			T23	193		T24	58		T25	83
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	2293302	1			T23	54		T24	90		T25	131
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	2043331	1			T23	214		T24	35		T25	13
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	534447	1			T23	166		T24	78		T25	77
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	549384	1			T24	68		T25	138		T26	182
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	289333	1			T23	170		T25	22		T26	19
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	532603	1			T23	170		T24	63		T25	69
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	2301339	1			T23	51		T24	87		T25	191
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	2040089	1			T23	213		T24	41		T25	16
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	535847	1			T23	190		T24	90		T25	47
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	545402	1			T24	62		T25	132		T26	89
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	287830	1			T23	166		T25	15		T26	7
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	531893	1			T23	154		T24	54		T25	49
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	2308000	1			T23	60		T24	98		T25	202
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	2031197	1			T23	157		T24	30		T25	19
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	536967	1			T23	190		T24	74		T25	78
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	545817	1			T24	70		T25	96		T26	120
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	288394	1			T23	156		T25	11		T26	11
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	532025	1			T23	211		T24	62		T25	44
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	2304394	1			T23	55		T24	103		T25	117
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	2032901	1			T23	200		T24	32		T25	17
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	535418	1			T23	156		T24	83		T25	56
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	547760	1			T24	54		T25	189		T26	135
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	290944	1			T23	235		T25	21		T26	22
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	530983	1			T23	128		T24	62		T25	50
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	2300147	1			T23	52		T24	102		T25	109
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	2037887	1			T23	278		T24	34		T25	22
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	534461	1			T23	180		T24	58		T25	51
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	547983	1			T24	90		T25	178		T26	177
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	287457	1			T23	112		T25	26		T26	13
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	534465	1			T23	152		T24	50		T25	64
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	2295607	1			T23	61		T24	101		T25	142
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	2045804	1			T23	247		T24	40		T25	29
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	533976	1			T23	130		T24	74		T25	51
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	545342	1			T24	76		T25	144		T26	174
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	290049	1			T23	198		T25	16		T26	30
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	531622	1			T23	138		T24	43		T25	68
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	2301156	1			T23	54		T24	93		T25	180
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	2040910	1			T23	235		T24	36		T25	17
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	534626	1			T23	134		T24	77		T25	83
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	544954	1			T24	76		T25	109		T26	84
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	289227	1			T23	169		T25	17		T26	27
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	531527	1			T23	182		T24	52		T25	44
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	2294729	1			T23	57		T24	110		T25	157
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	2042361	1			T23	242		T24	32		T25	18
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	537340	1			T23	168		T24	68		T25	39
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	547230	1			T24	72		T25	166		T26	175
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	290454	1			T23	167		T25	19		T26	28
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	530286	1			T23	140		T24	52		T25	51
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	2294483	1			T23	43		T24	107		T25	153
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	2043027	1			T23	220		T24	36		T25	20
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	536278	1			T23	196		T24	60		T25	90
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	548881	1			T24	67		T25	107		T26	118
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	290363	1			T23	142		T25	13		T26	9
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	529368	1			T23	173		T24	64		T25	67
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	2303338	1			T23	51		T24	107		T25	185
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	2040734	1			T23	206		T24	37		T25	13
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	536651	1			T23	154		T24	74		T25	80
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	545316	1			T24	46		T25	116		T26	143
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	287776	1			T23	180		T25	18		T26	20
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	528585	1			T23	183		T24	70		T25	38
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	2298915	1			T23	54		T24	102		T25	208
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	2044686	1			T23	249		T24	33		T25	25
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	539257	1			T23	172		T24	60		T25	83
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	541327	1			T24	86		T25	102		T26	131
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	287359	1			T23	146		T25	13		T26	22
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	530856	1			T23	153		T24	53		T25	19
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	2305365	1			T23	54		T24	92		T25	95
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	2031964	1			T23	201		T24	35		T25	16
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	536559	1			T23	199		T24	56		T25	94
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	549533	1			T24	62		T25	137		T26	162
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	289466	1			T23	162		T25	19		T26	24
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	529513	1			T23	158		T24	89		T25	89
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	2305484	1			T23	56		T24	103		T25	169
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	2035181	1			T23	207		T24	38		T25	28
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	533908	1			T23	168		T24	61		T25	108
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	545721	1			T24	84		T25	86		T26	143
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	289471	1			T23	206		T25	6		T26	27
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	532635	1			T23	137		T24	48		T25	53
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	2314236	1			T23	51		T24	107		T25	122
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	2026500	1			T23	216		T24	40		T25	13
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	533036	1			T23	180		T24	64		T25	35
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	549371	1			T24	58		T25	159		T26	92
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	290662	1			T23	194		T25	33		T26	9
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	528595	1			T23	133		T24	65		T25	88
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	2304262	1			T23	52		T24	86		T25	70
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	2042637	1			T23	279		T24	39		T25	10
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	534246	1			T23	132		T24	62		T25	91
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	546251	1			T24	69		T25	181		T26	104
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	288301	1			T23	171		T25	26		T26	14
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	526703	1			T23	140		T24	78		T25	72
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	2307811	1			T23	58		T24	114		T25	149
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	2032750	1			T23	274		T24	33		T25	9
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	534293	1			T23	166		T24	84		T25	43
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	545997	1			T24	47		T25	162		T26	165
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	291380	1			T23	162		T25	25		T26	21
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	530169	1			T23	114		T24	56		T25	62
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	2312503	1			T23	52		T24	115		T25	104
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	2028918	1			T23	209		T24	29		T25	17
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	531820	1			T23	181		T24	94		T25	72
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	549075	1			T24	54		T25	153		T26	133
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	290938	1			T23	176		T25	15		T26	13
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	529146	1			T23	156		T24	42		T25	89
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	2304461	1			T23	57		T24	93		T25	115
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	2037028	1			T23	225		T24	40		T25	2
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	532188	1			T23	180		T24	69		T25	41
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	546598	1			T24	72		T25	235		T26	182
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	290061	1			T23	132		T25	23		T26	27
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	532064	1			T23	180		T24	60		T25	34
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	2297793	1			T23	46		T24	100		T25	148
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	2040277	1			T23	233		T24	35		T25	20
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	532167	1			T23	128		T24	64		T25	65
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	552500	1			T24	50		T25	141		T26	177
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	289206	1			T23	214		T25	26		T26	24
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	530457	1			T23	153		T24	85		T25	50
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	2295872	1			T23	61		T24	99		T25	96
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	2048772	1			T23	200		T24	37		T25	13
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	533883	1			T23	142		T24	50		T25	70
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	547136	1			T24	74		T25	158		T26	177
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	288322	1			T23	180		T25	25		T26	28
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	528415	1			T23	191		T24	74		T25	88
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	2296602	1			T23	50		T24	103		T25	160
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	2047965	1			T23	231		T24	42		T25	12
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	535556	1			T23	189		T24	77		T25	24
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	546368	1			T24	44		T25	172		T26	152
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	288421	1			T23	120		T25	20		T26	19
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	527488	1			T23	184		T24	68		T25	62
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	2301018	1			T23	58		T24	108		T25	115
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	2039770	1			T23	269		T24	33		T25	13
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	532550	1			T23	156		T24	66		T25	60
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	549231	1			T24	72		T25	194		T26	163
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	290308	1			T23	155		T25	32		T26	23
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	529523	1			T23	136		T24	55		T25	36
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	2306028	1			T23	59		T24	111		T25	163
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	2037508	1			T23	224		T24	38		T25	26
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	533048	1			T23	196		T24	70		T25	90
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	546918	1			T24	65		T25	120		T26	145
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	292043	1			T23	154		T25	11		T26	18
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	526855	1			T23	141		T24	50		T25	40
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	2308291	1			T23	48		T24	98		T25	161
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	2035179	1			T23	221		T24	37		T25	13
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	531634	1			T23	198		T24	84		T25	40
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	549445	1			T24	54		T25	175		T26	149
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	289523	1			T23	153		T25	27		T26	26
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	528328	1			T23	154		T24	61		T25	34
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	2297136	1			T23	63		T24	118		T25	105
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	2046707	1			T23	210		T24	39		T25	11
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	535982	1			T23	138		T24	77		T25	16
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	545946	1			T24	48		T25	212		T26	175
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	288844	1			T23	176		T25	28		T26	34
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	527785	1			T23	187		T24	52		T25	78
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	2303249	1			T23	57		T24	124		T25	188
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	2036387	1			T23	198		T24	35		T25	22
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	530399	1			T23	144		T24	67		T25	46
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	549913	1			T24	46		T25	130		T26	200
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	292189	1			T23	171		T25	7		T26	22
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	530263	1			T23	204		T24	62		T25	57
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	2309739	1			T23	50		T24	82		T25	107
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	2036105	1			T23	187		T24	29		T25	13
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	532290	1			T23	178		T24	100		T25	54
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	545276	1			T24	58		T25	192		T26	122
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	288616	1			T23	176		T25	11		T26	17
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	530374	1			T23	183		T24	65		T25	73
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	2307528	1			T23	50		T24	114		T25	135
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	2036580	1			T23	239		T24	29		T25	15
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	534475	1			T23	129		T24	48		T25	56
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	548276	1			T24	75		T25	171		T26	189
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	287332	1			T23	176		T25	20		T26	29
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	528209	1			T23	180		T24	68		T25	53
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	2297663	1			T23	56		T24	93		T25	87
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	2045329	1			T23	197		T24	33		T25	25
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	533787	1			T23	173		T24	56		T25	89
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	548826	1			T24	84		T25	151		T26	144
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	289047	1			T23	164		T25	19		T26	28
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	527748	1			T23	184		T24	68		T25	79
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	2302088	1			T23	56		T24	128		T25	107
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	2036013	1			T23	221		T24	27		T25	10
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	533552	1			T23	210		T24	71		T25	59
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	550590	1			T24	58		T25	164		T26	139
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	290998	1			T23	145		T25	26		T26	23
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	529159	1			T23	142		T24	50		T25	84

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal