Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[1]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[2]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[3]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[4]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[5]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[6]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[7]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[8]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[9]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[10]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[11]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[12]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[13]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[14]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[15]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[16]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[17]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[18]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[19]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[20]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[21]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[22]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[23]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[24]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[25]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[26]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[27]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[28]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[29]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[30]	6242400	1			T23	774		T24	334		T25	450
bins_for_gpio_bits[31]	6242400	1			T23	774		T24	334		T25	450

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

108296606

1

T23

7142

T24

7623

T25

11303

auto[1]

91460194

1

T23

17626

T24

3065

T25

3097

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

108287245

1

T23

7148

T24

7614

T25

11295

auto[1]

91469555

1

T23

17620

T24

3074

T25

3105

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	3292091	1			T23	220		T24	209		T25	339
bins_for_gpio_bits[0]	auto[0]	auto[1]	96117	1			T23	44		T24	24		T25	12
bins_for_gpio_bits[0]	auto[1]	auto[0]	96386	1			T23	43		T24	24		T25	12
bins_for_gpio_bits[0]	auto[1]	auto[1]	2757806	1			T23	467		T24	77		T25	87
bins_for_gpio_bits[1]	auto[0]	auto[0]	3286675	1			T23	186		T24	228		T25	310
bins_for_gpio_bits[1]	auto[0]	auto[1]	95654	1			T23	44		T24	17		T25	12
bins_for_gpio_bits[1]	auto[1]	auto[0]	95907	1			T23	44		T24	17		T25	13
bins_for_gpio_bits[1]	auto[1]	auto[1]	2764164	1			T23	500		T24	72		T25	115
bins_for_gpio_bits[2]	auto[0]	auto[0]	3280845	1			T23	171		T24	216		T25	331
bins_for_gpio_bits[2]	auto[0]	auto[1]	95975	1			T23	49		T24	19		T25	14
bins_for_gpio_bits[2]	auto[1]	auto[0]	96288	1			T23	49		T24	20		T25	15
bins_for_gpio_bits[2]	auto[1]	auto[1]	2769292	1			T23	505		T24	79		T25	90
bins_for_gpio_bits[3]	auto[0]	auto[0]	3286306	1			T23	204		T24	223		T25	362
bins_for_gpio_bits[3]	auto[0]	auto[1]	95977	1			T23	37		T24	16		T25	8
bins_for_gpio_bits[3]	auto[1]	auto[0]	96282	1			T23	37		T24	16		T25	8
bins_for_gpio_bits[3]	auto[1]	auto[1]	2763835	1			T23	496		T24	79		T25	72
bins_for_gpio_bits[4]	auto[0]	auto[0]	3294532	1			T23	206		T24	226		T25	368
bins_for_gpio_bits[4]	auto[0]	auto[1]	95947	1			T23	44		T24	16		T25	8
bins_for_gpio_bits[4]	auto[1]	auto[0]	96252	1			T23	44		T24	16		T25	8
bins_for_gpio_bits[4]	auto[1]	auto[1]	2755669	1			T23	480		T24	76		T25	66
bins_for_gpio_bits[5]	auto[0]	auto[0]	3291378	1			T23	176		T24	224		T25	350
bins_for_gpio_bits[5]	auto[0]	auto[1]	95916	1			T23	35		T24	16		T25	12
bins_for_gpio_bits[5]	auto[1]	auto[0]	96194	1			T23	35		T24	16		T25	12
bins_for_gpio_bits[5]	auto[1]	auto[1]	2758912	1			T23	528		T24	78		T25	76
bins_for_gpio_bits[6]	auto[0]	auto[0]	3285995	1			T23	181		T24	234		T25	324
bins_for_gpio_bits[6]	auto[0]	auto[1]	96338	1			T23	51		T24	16		T25	14
bins_for_gpio_bits[6]	auto[1]	auto[0]	96596	1			T23	51		T24	16		T25	14
bins_for_gpio_bits[6]	auto[1]	auto[1]	2763471	1			T23	491		T24	68		T25	98
bins_for_gpio_bits[7]	auto[0]	auto[0]	3278530	1			T23	154		T24	234		T25	326
bins_for_gpio_bits[7]	auto[0]	auto[1]	96104	1			T23	37		T24	16		T25	10
bins_for_gpio_bits[7]	auto[1]	auto[0]	96395	1			T23	37		T24	17		T25	11
bins_for_gpio_bits[7]	auto[1]	auto[1]	2771371	1			T23	546		T24	67		T25	103
bins_for_gpio_bits[8]	auto[0]	auto[0]	3284281	1			T23	150		T24	232		T25	361
bins_for_gpio_bits[8]	auto[0]	auto[1]	96155	1			T23	38		T24	14		T25	11
bins_for_gpio_bits[8]	auto[1]	auto[0]	96455	1			T23	38		T24	14		T25	11
bins_for_gpio_bits[8]	auto[1]	auto[1]	2765509	1			T23	548		T24	74		T25	67
bins_for_gpio_bits[9]	auto[0]	auto[0]	3283166	1			T23	183		T24	233		T25	355
bins_for_gpio_bits[9]	auto[0]	auto[1]	95833	1			T23	42		T24	17		T25	7
bins_for_gpio_bits[9]	auto[1]	auto[0]	96133	1			T23	42		T24	17		T25	7
bins_for_gpio_bits[9]	auto[1]	auto[1]	2767268	1			T23	507		T24	67		T25	81
bins_for_gpio_bits[10]	auto[0]	auto[0]	3283196	1			T23	193		T24	216		T25	338
bins_for_gpio_bits[10]	auto[0]	auto[1]	96113	1			T23	46		T24	18		T25	12
bins_for_gpio_bits[10]	auto[1]	auto[0]	96446	1			T23	46		T24	18		T25	12
bins_for_gpio_bits[10]	auto[1]	auto[1]	2766645	1			T23	489		T24	82		T25	88
bins_for_gpio_bits[11]	auto[0]	auto[0]	3289119	1			T23	168		T24	213		T25	375
bins_for_gpio_bits[11]	auto[0]	auto[1]	95911	1			T23	37		T24	14		T25	6
bins_for_gpio_bits[11]	auto[1]	auto[0]	96186	1			T23	37		T24	14		T25	6
bins_for_gpio_bits[11]	auto[1]	auto[1]	2761184	1			T23	532		T24	93		T25	63
bins_for_gpio_bits[12]	auto[0]	auto[0]	3283057	1			T23	183		T24	232		T25	388
bins_for_gpio_bits[12]	auto[0]	auto[1]	96162	1			T23	43		T24	15		T25	5
bins_for_gpio_bits[12]	auto[1]	auto[0]	96442	1			T23	43		T24	16		T25	5
bins_for_gpio_bits[12]	auto[1]	auto[1]	2766739	1			T23	505		T24	71		T25	52
bins_for_gpio_bits[13]	auto[0]	auto[0]	3295141	1			T23	209		T24	188		T25	312
bins_for_gpio_bits[13]	auto[0]	auto[1]	95985	1			T23	45		T24	21		T25	14
bins_for_gpio_bits[13]	auto[1]	auto[0]	96316	1			T23	44		T24	22		T25	14
bins_for_gpio_bits[13]	auto[1]	auto[1]	2754958	1			T23	476		T24	103		T25	110
bins_for_gpio_bits[14]	auto[0]	auto[0]	3288993	1			T23	190		T24	234		T25	355
bins_for_gpio_bits[14]	auto[0]	auto[1]	95839	1			T23	34		T24	14		T25	8
bins_for_gpio_bits[14]	auto[1]	auto[0]	96120	1			T23	34		T24	14		T25	8
bins_for_gpio_bits[14]	auto[1]	auto[1]	2761448	1			T23	516		T24	72		T25	79
bins_for_gpio_bits[15]	auto[0]	auto[0]	3300498	1			T23	186		T24	210		T25	299
bins_for_gpio_bits[15]	auto[0]	auto[1]	95890	1			T23	45		T24	18		T25	17
bins_for_gpio_bits[15]	auto[1]	auto[0]	96145	1			T23	45		T24	19		T25	17
bins_for_gpio_bits[15]	auto[1]	auto[1]	2749867	1			T23	498		T24	87		T25	117
bins_for_gpio_bits[16]	auto[0]	auto[0]	3288180	1			T23	144		T24	198		T25	331
bins_for_gpio_bits[16]	auto[0]	auto[1]	96261	1			T23	40		T24	19		T25	11
bins_for_gpio_bits[16]	auto[1]	auto[0]	96579	1			T23	40		T24	19		T25	11
bins_for_gpio_bits[16]	auto[1]	auto[1]	2761380	1			T23	550		T24	98		T25	97
bins_for_gpio_bits[17]	auto[0]	auto[0]	3292326	1			T23	181		T24	229		T25	342
bins_for_gpio_bits[17]	auto[0]	auto[1]	95483	1			T23	43		T24	16		T25	11
bins_for_gpio_bits[17]	auto[1]	auto[0]	95775	1			T23	43		T24	16		T25	12
bins_for_gpio_bits[17]	auto[1]	auto[1]	2758816	1			T23	507		T24	73		T25	85
bins_for_gpio_bits[18]	auto[0]	auto[0]	3297589	1			T23	189		T24	250		T25	319
bins_for_gpio_bits[18]	auto[0]	auto[1]	95547	1			T23	45		T24	13		T25	10
bins_for_gpio_bits[18]	auto[1]	auto[0]	95809	1			T23	44		T24	13		T25	10
bins_for_gpio_bits[18]	auto[1]	auto[1]	2753455	1			T23	496		T24	58		T25	111
bins_for_gpio_bits[19]	auto[0]	auto[0]	3286713	1			T23	192		T24	219		T25	383
bins_for_gpio_bits[19]	auto[0]	auto[1]	96239	1			T23	45		T24	15		T25	8
bins_for_gpio_bits[19]	auto[1]	auto[0]	96534	1			T23	45		T24	15		T25	8
bins_for_gpio_bits[19]	auto[1]	auto[1]	2762914	1			T23	492		T24	85		T25	51
bins_for_gpio_bits[20]	auto[0]	auto[0]	3286119	1			T23	137		T24	200		T25	344
bins_for_gpio_bits[20]	auto[0]	auto[1]	96066	1			T23	37		T24	13		T25	10
bins_for_gpio_bits[20]	auto[1]	auto[0]	96341	1			T23	37		T24	14		T25	10
bins_for_gpio_bits[20]	auto[1]	auto[1]	2763874	1			T23	563		T24	107		T25	86
bins_for_gpio_bits[21]	auto[0]	auto[0]	3280668	1			T23	166		T24	206		T25	309
bins_for_gpio_bits[21]	auto[0]	auto[1]	95905	1			T23	37		T24	17		T25	14
bins_for_gpio_bits[21]	auto[1]	auto[0]	96223	1			T23	37		T24	17		T25	15
bins_for_gpio_bits[21]	auto[1]	auto[1]	2769604	1			T23	534		T24	94		T25	112
bins_for_gpio_bits[22]	auto[0]	auto[0]	3282022	1			T23	190		T24	209		T25	349
bins_for_gpio_bits[22]	auto[0]	auto[1]	96218	1			T23	50		T24	15		T25	7
bins_for_gpio_bits[22]	auto[1]	auto[0]	96504	1			T23	49		T24	15		T25	7
bins_for_gpio_bits[22]	auto[1]	auto[1]	2767656	1			T23	485		T24	95		T25	87
bins_for_gpio_bits[23]	auto[0]	auto[0]	3286848	1			T23	172		T24	231		T25	364
bins_for_gpio_bits[23]	auto[0]	auto[1]	95623	1			T23	42		T24	14		T25	5
bins_for_gpio_bits[23]	auto[1]	auto[0]	95951	1			T23	42		T24	15		T25	5
bins_for_gpio_bits[23]	auto[1]	auto[1]	2763978	1			T23	518		T24	74		T25	76
bins_for_gpio_bits[24]	auto[0]	auto[0]	3289890	1			T23	206		T24	228		T25	364
bins_for_gpio_bits[24]	auto[0]	auto[1]	95815	1			T23	49		T24	18		T25	9
bins_for_gpio_bits[24]	auto[1]	auto[0]	96104	1			T23	49		T24	18		T25	9
bins_for_gpio_bits[24]	auto[1]	auto[1]	2760591	1			T23	470		T24	70		T25	68
bins_for_gpio_bits[25]	auto[0]	auto[0]	3293067	1			T23	201		T24	218		T25	370
bins_for_gpio_bits[25]	auto[0]	auto[1]	96007	1			T23	45		T24	17		T25	6
bins_for_gpio_bits[25]	auto[1]	auto[0]	96303	1			T23	45		T24	18		T25	6
bins_for_gpio_bits[25]	auto[1]	auto[1]	2757023	1			T23	483		T24	81		T25	68
bins_for_gpio_bits[26]	auto[0]	auto[0]	3283129	1			T23	168		T24	229		T25	323
bins_for_gpio_bits[26]	auto[0]	auto[1]	95658	1			T23	33		T24	14		T25	10
bins_for_gpio_bits[26]	auto[1]	auto[0]	95935	1			T23	33		T24	14		T25	10
bins_for_gpio_bits[26]	auto[1]	auto[1]	2767678	1			T23	540		T24	77		T25	107
bins_for_gpio_bits[27]	auto[0]	auto[0]	3287644	1			T23	159		T24	221		T25	356
bins_for_gpio_bits[27]	auto[0]	auto[1]	95631	1			T23	42		T24	16		T25	8
bins_for_gpio_bits[27]	auto[1]	auto[0]	95917	1			T23	42		T24	16		T25	8
bins_for_gpio_bits[27]	auto[1]	auto[1]	2763208	1			T23	531		T24	81		T25	78
bins_for_gpio_bits[28]	auto[0]	auto[0]	3291092	1			T23	186		T24	224		T25	343
bins_for_gpio_bits[28]	auto[0]	auto[1]	95886	1			T23	42		T24	15		T25	9
bins_for_gpio_bits[28]	auto[1]	auto[0]	96213	1			T23	42		T24	16		T25	10
bins_for_gpio_bits[28]	auto[1]	auto[1]	2759209	1			T23	504		T24	79		T25	88
bins_for_gpio_bits[29]	auto[0]	auto[0]	3294021	1			T23	146		T24	218		T25	351
bins_for_gpio_bits[29]	auto[0]	auto[1]	95986	1			T23	34		T24	19		T25	11
bins_for_gpio_bits[29]	auto[1]	auto[0]	96258	1			T23	33		T24	19		T25	11
bins_for_gpio_bits[29]	auto[1]	auto[1]	2756135	1			T23	561		T24	78		T25	77
bins_for_gpio_bits[30]	auto[0]	auto[0]	3283978	1			T23	186		T24	219		T25	316
bins_for_gpio_bits[30]	auto[0]	auto[1]	95969	1			T23	44		T24	14		T25	10
bins_for_gpio_bits[30]	auto[1]	auto[0]	96298	1			T23	43		T24	14		T25	11
bins_for_gpio_bits[30]	auto[1]	auto[1]	2766155	1			T23	501		T24	87		T25	113
bins_for_gpio_bits[31]	auto[0]	auto[0]	3289910	1			T23	226		T24	240		T25	317
bins_for_gpio_bits[31]	auto[0]	auto[1]	96036	1			T23	40		T24	17		T25	12
bins_for_gpio_bits[31]	auto[1]	auto[0]	96320	1			T23	40		T24	17		T25	13
bins_for_gpio_bits[31]	auto[1]	auto[1]	2760134	1			T23	468		T24	60		T25	108