Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4164352 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
2146681 |
1 |
|
|
T27 |
32 |
|
T29 |
110 |
|
T31 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6040446 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
270587 |
1 |
|
|
T27 |
2 |
|
T29 |
37 |
|
T33 |
49 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4180226 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
2130807 |
1 |
|
|
T27 |
55 |
|
T29 |
162 |
|
T31 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
933309 |
1 |
|
|
T27 |
33 |
|
T29 |
84 |
|
T31 |
3 |
| auto[1] |
auto[0] |
auto[1] |
136516 |
1 |
|
|
T27 |
2 |
|
T29 |
27 |
|
T33 |
21 |
| auto[1] |
auto[1] |
auto[0] |
926911 |
1 |
|
|
T27 |
20 |
|
T29 |
41 |
|
T33 |
613 |
| auto[1] |
auto[1] |
auto[1] |
134071 |
1 |
|
|
T29 |
10 |
|
T33 |
28 |
|
T34 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4171734 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
2139299 |
1 |
|
|
T27 |
34 |
|
T29 |
151 |
|
T31 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6039385 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
271648 |
1 |
|
|
T27 |
3 |
|
T29 |
38 |
|
T33 |
41 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4164233 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
2146800 |
1 |
|
|
T27 |
38 |
|
T29 |
181 |
|
T31 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
936954 |
1 |
|
|
T27 |
26 |
|
T29 |
105 |
|
T33 |
698 |
| auto[1] |
auto[0] |
auto[1] |
135564 |
1 |
|
|
T27 |
2 |
|
T29 |
30 |
|
T33 |
30 |
| auto[1] |
auto[1] |
auto[0] |
938198 |
1 |
|
|
T27 |
9 |
|
T29 |
38 |
|
T31 |
4 |
| auto[1] |
auto[1] |
auto[1] |
136084 |
1 |
|
|
T27 |
1 |
|
T29 |
8 |
|
T33 |
11 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4168165 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
2142868 |
1 |
|
|
T27 |
49 |
|
T29 |
225 |
|
T31 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6038298 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
272735 |
1 |
|
|
T27 |
6 |
|
T29 |
37 |
|
T33 |
46 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4165760 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
2145273 |
1 |
|
|
T27 |
46 |
|
T29 |
194 |
|
T31 |
15 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
943216 |
1 |
|
|
T27 |
16 |
|
T29 |
61 |
|
T31 |
11 |
| auto[1] |
auto[0] |
auto[1] |
136946 |
1 |
|
|
T27 |
4 |
|
T29 |
13 |
|
T33 |
19 |
| auto[1] |
auto[1] |
auto[0] |
929322 |
1 |
|
|
T27 |
24 |
|
T29 |
96 |
|
T31 |
4 |
| auto[1] |
auto[1] |
auto[1] |
135789 |
1 |
|
|
T27 |
2 |
|
T29 |
24 |
|
T33 |
27 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4160760 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
2150273 |
1 |
|
|
T27 |
41 |
|
T29 |
125 |
|
T31 |
7 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6036347 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
274686 |
1 |
|
|
T27 |
4 |
|
T29 |
25 |
|
T33 |
41 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4157605 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
2153428 |
1 |
|
|
T27 |
45 |
|
T29 |
155 |
|
T31 |
11 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
939081 |
1 |
|
|
T27 |
31 |
|
T29 |
72 |
|
T31 |
4 |
| auto[1] |
auto[0] |
auto[1] |
136916 |
1 |
|
|
T27 |
3 |
|
T29 |
14 |
|
T33 |
22 |
| auto[1] |
auto[1] |
auto[0] |
939661 |
1 |
|
|
T27 |
10 |
|
T29 |
58 |
|
T31 |
7 |
| auto[1] |
auto[1] |
auto[1] |
137770 |
1 |
|
|
T27 |
1 |
|
T29 |
11 |
|
T33 |
19 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4156145 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
2154888 |
1 |
|
|
T27 |
53 |
|
T29 |
70 |
|
T31 |
9 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6037000 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
274033 |
1 |
|
|
T27 |
7 |
|
T29 |
31 |
|
T33 |
53 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4157394 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
2153639 |
1 |
|
|
T27 |
64 |
|
T29 |
172 |
|
T31 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
933416 |
1 |
|
|
T27 |
27 |
|
T29 |
112 |
|
T31 |
7 |
| auto[1] |
auto[0] |
auto[1] |
135698 |
1 |
|
|
T27 |
4 |
|
T29 |
26 |
|
T33 |
26 |
| auto[1] |
auto[1] |
auto[0] |
946190 |
1 |
|
|
T27 |
30 |
|
T29 |
29 |
|
T31 |
1 |
| auto[1] |
auto[1] |
auto[1] |
138335 |
1 |
|
|
T27 |
3 |
|
T29 |
5 |
|
T33 |
27 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4155007 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
2156026 |
1 |
|
|
T27 |
68 |
|
T29 |
293 |
|
T31 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6038882 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
272151 |
1 |
|
|
T27 |
4 |
|
T29 |
38 |
|
T33 |
43 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4165171 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
2145862 |
1 |
|
|
T27 |
43 |
|
T29 |
176 |
|
T31 |
11 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
936425 |
1 |
|
|
T27 |
14 |
|
T29 |
76 |
|
T31 |
11 |
| auto[1] |
auto[0] |
auto[1] |
135561 |
1 |
|
|
T27 |
2 |
|
T29 |
20 |
|
T33 |
17 |
| auto[1] |
auto[1] |
auto[0] |
937286 |
1 |
|
|
T27 |
25 |
|
T29 |
62 |
|
T33 |
584 |
| auto[1] |
auto[1] |
auto[1] |
136590 |
1 |
|
|
T27 |
2 |
|
T29 |
18 |
|
T33 |
26 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4177745 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
2133288 |
1 |
|
|
T27 |
20 |
|
T29 |
284 |
|
T31 |
4 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6039285 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
271748 |
1 |
|
|
T27 |
5 |
|
T29 |
28 |
|
T33 |
42 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4170411 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
2140622 |
1 |
|
|
T27 |
74 |
|
T29 |
134 |
|
T31 |
15 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
941751 |
1 |
|
|
T27 |
51 |
|
T29 |
19 |
|
T31 |
11 |
| auto[1] |
auto[0] |
auto[1] |
138128 |
1 |
|
|
T27 |
3 |
|
T29 |
4 |
|
T33 |
21 |
| auto[1] |
auto[1] |
auto[0] |
927123 |
1 |
|
|
T27 |
18 |
|
T29 |
87 |
|
T31 |
4 |
| auto[1] |
auto[1] |
auto[1] |
133620 |
1 |
|
|
T27 |
2 |
|
T29 |
24 |
|
T33 |
21 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4168465 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
2142568 |
1 |
|
|
T27 |
57 |
|
T29 |
220 |
|
T33 |
1046 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6041393 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
269640 |
1 |
|
|
T27 |
4 |
|
T29 |
42 |
|
T33 |
44 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4184105 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
2126928 |
1 |
|
|
T27 |
64 |
|
T29 |
234 |
|
T33 |
1184 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
934618 |
1 |
|
|
T27 |
18 |
|
T29 |
71 |
|
T33 |
634 |
| auto[1] |
auto[0] |
auto[1] |
135424 |
1 |
|
|
T27 |
1 |
|
T29 |
16 |
|
T33 |
20 |
| auto[1] |
auto[1] |
auto[0] |
922670 |
1 |
|
|
T27 |
42 |
|
T29 |
121 |
|
T33 |
506 |
| auto[1] |
auto[1] |
auto[1] |
134216 |
1 |
|
|
T27 |
3 |
|
T29 |
26 |
|
T33 |
24 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4158105 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
2152928 |
1 |
|
|
T27 |
58 |
|
T29 |
268 |
|
T33 |
1144 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6036673 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
274360 |
1 |
|
|
T27 |
6 |
|
T29 |
51 |
|
T33 |
47 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4154323 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
2156710 |
1 |
|
|
T27 |
68 |
|
T29 |
282 |
|
T31 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
943085 |
1 |
|
|
T27 |
34 |
|
T29 |
63 |
|
T31 |
8 |
| auto[1] |
auto[0] |
auto[1] |
137434 |
1 |
|
|
T27 |
3 |
|
T29 |
17 |
|
T33 |
20 |
| auto[1] |
auto[1] |
auto[0] |
939265 |
1 |
|
|
T27 |
28 |
|
T29 |
168 |
|
T33 |
560 |
| auto[1] |
auto[1] |
auto[1] |
136926 |
1 |
|
|
T27 |
3 |
|
T29 |
34 |
|
T33 |
27 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4178419 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
2132614 |
1 |
|
|
T27 |
15 |
|
T29 |
294 |
|
T31 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6038504 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
272529 |
1 |
|
|
T27 |
6 |
|
T29 |
42 |
|
T33 |
37 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4163264 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
2147769 |
1 |
|
|
T27 |
67 |
|
T29 |
208 |
|
T31 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
944318 |
1 |
|
|
T27 |
52 |
|
T29 |
24 |
|
T31 |
3 |
| auto[1] |
auto[0] |
auto[1] |
137360 |
1 |
|
|
T27 |
5 |
|
T29 |
6 |
|
T33 |
15 |
| auto[1] |
auto[1] |
auto[0] |
930922 |
1 |
|
|
T27 |
9 |
|
T29 |
142 |
|
T33 |
625 |
| auto[1] |
auto[1] |
auto[1] |
135169 |
1 |
|
|
T27 |
1 |
|
T29 |
36 |
|
T33 |
22 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4156264 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
2154769 |
1 |
|
|
T27 |
48 |
|
T29 |
253 |
|
T31 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6040811 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
270222 |
1 |
|
|
T27 |
3 |
|
T29 |
44 |
|
T33 |
56 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4181049 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
2129984 |
1 |
|
|
T27 |
39 |
|
T29 |
206 |
|
T33 |
1369 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
929042 |
1 |
|
|
T27 |
21 |
|
T29 |
50 |
|
T33 |
738 |
| auto[1] |
auto[0] |
auto[1] |
134792 |
1 |
|
|
T27 |
3 |
|
T29 |
14 |
|
T33 |
29 |
| auto[1] |
auto[1] |
auto[0] |
930720 |
1 |
|
|
T27 |
15 |
|
T29 |
112 |
|
T33 |
575 |
| auto[1] |
auto[1] |
auto[1] |
135430 |
1 |
|
|
T29 |
30 |
|
T33 |
27 |
|
T34 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4157209 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
2153824 |
1 |
|
|
T27 |
42 |
|
T29 |
287 |
|
T31 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6037201 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
273832 |
1 |
|
|
T29 |
56 |
|
T33 |
36 |
|
T34 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4159788 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
2151245 |
1 |
|
|
T27 |
11 |
|
T29 |
241 |
|
T31 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
943602 |
1 |
|
|
T27 |
8 |
|
T29 |
87 |
|
T31 |
3 |
| auto[1] |
auto[0] |
auto[1] |
137889 |
1 |
|
|
T29 |
33 |
|
T33 |
18 |
|
T34 |
2 |
| auto[1] |
auto[1] |
auto[0] |
933811 |
1 |
|
|
T27 |
3 |
|
T29 |
98 |
|
T33 |
534 |
| auto[1] |
auto[1] |
auto[1] |
135943 |
1 |
|
|
T29 |
23 |
|
T33 |
18 |
|
T34 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4168746 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
2142287 |
1 |
|
|
T27 |
63 |
|
T29 |
217 |
|
T31 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6039605 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
271428 |
1 |
|
|
T27 |
4 |
|
T29 |
18 |
|
T33 |
50 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4173794 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
2137239 |
1 |
|
|
T27 |
40 |
|
T29 |
75 |
|
T31 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
939196 |
1 |
|
|
T27 |
10 |
|
T29 |
33 |
|
T33 |
709 |
| auto[1] |
auto[0] |
auto[1] |
136381 |
1 |
|
|
T29 |
10 |
|
T33 |
28 |
|
T34 |
8 |
| auto[1] |
auto[1] |
auto[0] |
926615 |
1 |
|
|
T27 |
26 |
|
T29 |
24 |
|
T31 |
3 |
| auto[1] |
auto[1] |
auto[1] |
135047 |
1 |
|
|
T27 |
4 |
|
T29 |
8 |
|
T33 |
22 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4163266 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
2147767 |
1 |
|
|
T27 |
55 |
|
T29 |
192 |
|
T31 |
8 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6038138 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
272895 |
1 |
|
|
T27 |
4 |
|
T29 |
34 |
|
T33 |
51 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4162675 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
2148358 |
1 |
|
|
T27 |
56 |
|
T29 |
183 |
|
T31 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
941600 |
1 |
|
|
T27 |
23 |
|
T29 |
64 |
|
T31 |
5 |
| auto[1] |
auto[0] |
auto[1] |
136863 |
1 |
|
|
T27 |
2 |
|
T29 |
16 |
|
T33 |
24 |
| auto[1] |
auto[1] |
auto[0] |
933863 |
1 |
|
|
T27 |
29 |
|
T29 |
85 |
|
T31 |
3 |
| auto[1] |
auto[1] |
auto[1] |
136032 |
1 |
|
|
T27 |
2 |
|
T29 |
18 |
|
T33 |
27 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4155419 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
2155614 |
1 |
|
|
T27 |
71 |
|
T29 |
175 |
|
T31 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6038119 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
272914 |
1 |
|
|
T27 |
4 |
|
T29 |
30 |
|
T33 |
38 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4166696 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
2144337 |
1 |
|
|
T27 |
60 |
|
T29 |
164 |
|
T31 |
12 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
935352 |
1 |
|
|
T27 |
15 |
|
T29 |
57 |
|
T31 |
8 |
| auto[1] |
auto[0] |
auto[1] |
136473 |
1 |
|
|
T27 |
1 |
|
T29 |
12 |
|
T33 |
19 |
| auto[1] |
auto[1] |
auto[0] |
936071 |
1 |
|
|
T27 |
41 |
|
T29 |
77 |
|
T31 |
4 |
| auto[1] |
auto[1] |
auto[1] |
136441 |
1 |
|
|
T27 |
3 |
|
T29 |
18 |
|
T33 |
19 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4167773 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
2143260 |
1 |
|
|
T27 |
45 |
|
T29 |
292 |
|
T31 |
8 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6036687 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
274346 |
1 |
|
|
T27 |
10 |
|
T29 |
22 |
|
T33 |
45 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4156648 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
2154385 |
1 |
|
|
T27 |
75 |
|
T29 |
100 |
|
T31 |
12 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
944734 |
1 |
|
|
T27 |
35 |
|
T29 |
12 |
|
T31 |
5 |
| auto[1] |
auto[0] |
auto[1] |
137543 |
1 |
|
|
T27 |
6 |
|
T29 |
3 |
|
T33 |
22 |
| auto[1] |
auto[1] |
auto[0] |
935305 |
1 |
|
|
T27 |
30 |
|
T29 |
66 |
|
T31 |
7 |
| auto[1] |
auto[1] |
auto[1] |
136803 |
1 |
|
|
T27 |
4 |
|
T29 |
19 |
|
T33 |
23 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4160507 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
2150526 |
1 |
|
|
T27 |
53 |
|
T29 |
220 |
|
T31 |
8 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6039923 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
271110 |
1 |
|
|
T27 |
3 |
|
T29 |
32 |
|
T33 |
44 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4167691 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
2143342 |
1 |
|
|
T27 |
53 |
|
T29 |
177 |
|
T33 |
1201 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
935894 |
1 |
|
|
T27 |
28 |
|
T29 |
97 |
|
T33 |
570 |
| auto[1] |
auto[0] |
auto[1] |
135560 |
1 |
|
|
T27 |
1 |
|
T29 |
24 |
|
T33 |
21 |
| auto[1] |
auto[1] |
auto[0] |
936338 |
1 |
|
|
T27 |
22 |
|
T29 |
48 |
|
T33 |
587 |
| auto[1] |
auto[1] |
auto[1] |
135550 |
1 |
|
|
T27 |
2 |
|
T29 |
8 |
|
T33 |
23 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |