Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4158061 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
2152972 |
1 |
|
|
T27 |
45 |
|
T29 |
107 |
|
T31 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6039199 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
271834 |
1 |
|
|
T27 |
2 |
|
T29 |
52 |
|
T33 |
45 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4171287 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
2139746 |
1 |
|
|
T27 |
37 |
|
T29 |
268 |
|
T31 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
932789 |
1 |
|
|
T27 |
15 |
|
T29 |
184 |
|
T31 |
3 |
| auto[1] |
auto[0] |
auto[1] |
135313 |
1 |
|
|
T27 |
1 |
|
T29 |
45 |
|
T33 |
20 |
| auto[1] |
auto[1] |
auto[0] |
935123 |
1 |
|
|
T27 |
20 |
|
T29 |
32 |
|
T31 |
4 |
| auto[1] |
auto[1] |
auto[1] |
136521 |
1 |
|
|
T27 |
1 |
|
T29 |
7 |
|
T33 |
25 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |