Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4168465 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
2142568 |
1 |
|
|
T27 |
57 |
|
T29 |
220 |
|
T33 |
1046 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5329916 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
981117 |
1 |
|
|
T27 |
24 |
|
T29 |
41 |
|
T31 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4172663 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
2138370 |
1 |
|
|
T27 |
57 |
|
T29 |
100 |
|
T31 |
6 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
580104 |
1 |
|
|
T27 |
17 |
|
T29 |
10 |
|
T33 |
544 |
| auto[1] |
auto[0] |
auto[1] |
488877 |
1 |
|
|
T27 |
11 |
|
T29 |
11 |
|
T31 |
6 |
| auto[1] |
auto[1] |
auto[0] |
577149 |
1 |
|
|
T27 |
16 |
|
T29 |
49 |
|
T33 |
437 |
| auto[1] |
auto[1] |
auto[1] |
492240 |
1 |
|
|
T27 |
13 |
|
T29 |
30 |
|
T33 |
145 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |