Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4178419 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
2132614 |
1 |
|
|
T27 |
15 |
|
T29 |
294 |
|
T31 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5329144 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
981889 |
1 |
|
|
T27 |
15 |
|
T29 |
88 |
|
T33 |
330 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4164652 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
2146381 |
1 |
|
|
T27 |
25 |
|
T29 |
160 |
|
T31 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
593937 |
1 |
|
|
T27 |
10 |
|
T29 |
22 |
|
T31 |
3 |
| auto[1] |
auto[0] |
auto[1] |
498567 |
1 |
|
|
T27 |
13 |
|
T29 |
32 |
|
T33 |
159 |
| auto[1] |
auto[1] |
auto[0] |
570555 |
1 |
|
|
T29 |
50 |
|
T31 |
1 |
|
T33 |
392 |
| auto[1] |
auto[1] |
auto[1] |
483322 |
1 |
|
|
T27 |
2 |
|
T29 |
56 |
|
T33 |
171 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |