Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4156695 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
2154338 |
1 |
|
|
T27 |
33 |
|
T29 |
175 |
|
T31 |
9 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6039128 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
271905 |
1 |
|
|
T27 |
7 |
|
T29 |
53 |
|
T33 |
42 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4168118 |
1 |
|
|
T23 |
442 |
|
T24 |
202 |
|
T25 |
231 |
| auto[1] |
2142915 |
1 |
|
|
T27 |
64 |
|
T29 |
256 |
|
T31 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
935101 |
1 |
|
|
T27 |
34 |
|
T29 |
135 |
|
T33 |
509 |
| auto[1] |
auto[0] |
auto[1] |
135535 |
1 |
|
|
T27 |
6 |
|
T29 |
33 |
|
T33 |
16 |
| auto[1] |
auto[1] |
auto[0] |
935909 |
1 |
|
|
T27 |
23 |
|
T29 |
68 |
|
T31 |
7 |
| auto[1] |
auto[1] |
auto[1] |
136370 |
1 |
|
|
T27 |
1 |
|
T29 |
20 |
|
T33 |
26 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |