Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1534478	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5392197

1

T33

136

T34

169

T35

270

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3106051	1			T33	124		T34	120		T35	59
values[0x0]	1903925	1			T33	37		T34	59		T35	111
values[0x1]	1916699	1			T33	43		T34	51		T35	127

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1220410	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5706265

1

T33

150

T34

181

T35

273

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	22822	1			T35	1		T38	1		T22	4
valid_sources[0x01]	20146	1			T38	2		T22	5		T24	1
valid_sources[0x02]	20829	1			T33	3		T37	23		T38	3
valid_sources[0x03]	22458	1			T38	5		T20	1		T22	2
valid_sources[0x04]	20288	1			T35	1		T38	4		T22	5
valid_sources[0x05]	21998	1			T33	3		T35	1		T36	101
valid_sources[0x06]	20659	1			T35	1		T38	3		T22	5
valid_sources[0x07]	21817	1			T38	1		T22	1		T25	3
valid_sources[0x08]	23755	1			T35	1		T38	1		T20	6
valid_sources[0x09]	20390	1			T35	1		T38	2		T20	6
valid_sources[0x0a]	21053	1			T35	1		T38	7		T22	5
valid_sources[0x0b]	21210	1			T35	2		T38	2		T20	1
valid_sources[0x0c]	21886	1			T38	3		T22	4		T24	3
valid_sources[0x0d]	22204	1			T33	1		T34	230		T35	2
valid_sources[0x0e]	20547	1			T35	1		T38	3		T20	2
valid_sources[0x0f]	20836	1			T35	1		T38	6		T20	9
valid_sources[0x10]	20110	1			T35	2		T38	2		T22	2
valid_sources[0x11]	20147	1			T35	5		T24	4		T25	1
valid_sources[0x12]	20459	1			T35	2		T38	3		T22	6
valid_sources[0x13]	27480	1			T35	2		T38	5		T22	7
valid_sources[0x14]	24512	1			T35	1		T38	3		T22	5
valid_sources[0x15]	25515	1			T38	3		T22	1		T24	5
valid_sources[0x16]	20469	1			T38	2		T20	5		T22	8
valid_sources[0x17]	20498	1			T38	3		T22	3		T24	3
valid_sources[0x18]	23447	1			T38	1		T22	3		T25	2
valid_sources[0x19]	24056	1			T33	2		T35	1		T38	6
valid_sources[0x1a]	20631	1			T35	1		T37	29		T38	1
valid_sources[0x1b]	23724	1			T35	1		T38	3		T22	6
valid_sources[0x1c]	24342	1			T35	1		T38	2		T22	1
valid_sources[0x1d]	27932	1			T33	1		T38	1		T22	4
valid_sources[0x1e]	26158	1			T33	2		T35	1		T38	3
valid_sources[0x1f]	20448	1			T35	2		T38	2		T20	9
valid_sources[0x20]	20843	1			T35	1		T38	6		T22	2
valid_sources[0x21]	24067	1			T35	2		T38	3		T22	7
valid_sources[0x22]	21831	1			T38	4		T22	4		T24	2
valid_sources[0x23]	20320	1			T35	1		T38	2		T20	1
valid_sources[0x24]	269708	1			T38	1		T22	3		T28	2
valid_sources[0x25]	20487	1			T38	2		T22	2		T24	1
valid_sources[0x26]	30995	1			T35	2		T38	3		T22	7
valid_sources[0x27]	21115	1			T33	3		T35	4		T38	5
valid_sources[0x28]	22380	1			T35	3		T38	3		T22	3
valid_sources[0x29]	20724	1			T33	2		T38	1		T22	1
valid_sources[0x2a]	20548	1			T35	1		T38	4		T20	1
valid_sources[0x2b]	23108	1			T35	3		T37	14		T38	1
valid_sources[0x2c]	20092	1			T35	1		T38	3		T22	3
valid_sources[0x2d]	21736	1			T35	2		T38	5		T22	7
valid_sources[0x2e]	21793	1			T35	1		T38	2		T22	3
valid_sources[0x2f]	20394	1			T35	2		T38	3		T22	2
valid_sources[0x30]	21351	1			T38	3		T20	2		T22	5
valid_sources[0x31]	21399	1			T35	1		T38	4		T24	1
valid_sources[0x32]	20975	1			T33	6		T38	3		T39	897
valid_sources[0x33]	22030	1			T38	1		T22	4		T24	3
valid_sources[0x34]	21668	1			T38	2		T20	13		T22	5
valid_sources[0x35]	21135	1			T35	1		T38	1		T22	2
valid_sources[0x36]	21040	1			T38	3		T22	3		T24	2
valid_sources[0x37]	20839	1			T35	4		T38	1		T20	4
valid_sources[0x38]	20096	1			T35	4		T38	1		T20	3
valid_sources[0x39]	25118	1			T38	2		T22	1		T24	4
valid_sources[0x3a]	20864	1			T35	2		T38	1		T22	2
valid_sources[0x3b]	19846	1			T35	1		T38	2		T20	2
valid_sources[0x3c]	20688	1			T35	2		T38	5		T22	5
valid_sources[0x3d]	22290	1			T35	1		T38	6		T20	4
valid_sources[0x3e]	19722	1			T35	1		T38	3		T22	3
valid_sources[0x3f]	19741	1			T33	8		T35	3		T38	4
valid_sources[0x40]	22882	1			T33	3		T35	4		T22	2
valid_sources[0x41]	20293	1			T33	1		T38	2		T22	6
valid_sources[0x42]	21078	1			T33	3		T38	2		T22	4
valid_sources[0x43]	21189	1			T35	5		T38	3		T20	1
valid_sources[0x44]	23140	1			T38	5		T20	1		T22	1
valid_sources[0x45]	20589	1			T38	3		T22	3		T24	9
valid_sources[0x46]	19979	1			T35	1		T37	6		T38	2
valid_sources[0x47]	19982	1			T35	2		T38	3		T22	7
valid_sources[0x48]	25655	1			T35	1		T38	6		T22	2
valid_sources[0x49]	22043	1			T33	1		T35	2		T38	2
valid_sources[0x4a]	21088	1			T35	1		T38	4		T20	6
valid_sources[0x4b]	20197	1			T35	2		T38	5		T22	1
valid_sources[0x4c]	20739	1			T35	1		T38	5		T22	6
valid_sources[0x4d]	22797	1			T38	4		T22	2		T25	1
valid_sources[0x4e]	23213	1			T35	3		T38	1		T22	1
valid_sources[0x4f]	150529	1			T38	2		T20	11		T22	2
valid_sources[0x50]	25043	1			T38	1		T22	2		T29	1
valid_sources[0x51]	22486	1			T35	3		T38	6		T22	1
valid_sources[0x52]	24741	1			T35	1		T38	2		T22	2
valid_sources[0x53]	22162	1			T33	3		T38	1		T22	3
valid_sources[0x54]	22211	1			T35	1		T38	5		T22	2
valid_sources[0x55]	20358	1			T35	2		T38	3		T22	2
valid_sources[0x56]	20305	1			T35	1		T38	3		T22	5
valid_sources[0x57]	22853	1			T38	3		T22	2		T24	1
valid_sources[0x58]	23984	1			T33	1		T35	4		T38	1
valid_sources[0x59]	20082	1			T35	2		T38	3		T22	1
valid_sources[0x5a]	19630	1			T38	2		T22	2		T24	5
valid_sources[0x5b]	22689	1			T33	10		T35	1		T38	1
valid_sources[0x5c]	26205	1			T22	4		T24	2		T25	2
valid_sources[0x5d]	55309	1			T35	2		T37	26		T38	6
valid_sources[0x5e]	21185	1			T38	3		T22	1		T24	2
valid_sources[0x5f]	19469	1			T35	1		T38	3		T20	1
valid_sources[0x60]	20794	1			T35	1		T38	5		T22	1
valid_sources[0x61]	22350	1			T38	3		T22	6		T24	5
valid_sources[0x62]	21157	1			T35	1		T38	3		T20	1
valid_sources[0x63]	27631	1			T38	2		T24	4		T25	2
valid_sources[0x64]	20541	1			T38	4		T22	6		T24	7
valid_sources[0x65]	23681	1			T33	2		T35	1		T20	2
valid_sources[0x66]	20025	1			T35	2		T37	36		T22	1
valid_sources[0x67]	22631	1			T33	4		T37	24		T38	2
valid_sources[0x68]	20273	1			T33	2		T35	2		T38	1
valid_sources[0x69]	19618	1			T33	3		T35	1		T38	1
valid_sources[0x6a]	24017	1			T35	1		T38	2		T22	1
valid_sources[0x6b]	22406	1			T35	2		T38	2		T20	1
valid_sources[0x6c]	20262	1			T35	2		T38	4		T22	3
valid_sources[0x6d]	24199	1			T35	1		T37	17		T38	4
valid_sources[0x6e]	21910	1			T35	2		T38	3		T20	5
valid_sources[0x6f]	22582	1			T20	9		T22	4		T25	2
valid_sources[0x70]	21291	1			T35	1		T38	2		T22	4
valid_sources[0x71]	21236	1			T35	1		T38	2		T20	1
valid_sources[0x72]	25257	1			T35	2		T38	5		T22	4
valid_sources[0x73]	24090	1			T33	3		T35	2		T38	1
valid_sources[0x74]	20993	1			T33	4		T35	3		T37	17
valid_sources[0x75]	32297	1			T38	7		T20	2		T24	4
valid_sources[0x76]	24992	1			T38	2		T20	9		T22	5
valid_sources[0x77]	20192	1			T35	3		T38	3		T20	3
valid_sources[0x78]	21780	1			T35	1		T38	3		T22	3
valid_sources[0x79]	162728	1			T35	2		T38	2		T22	5
valid_sources[0x7a]	20369	1			T38	2		T20	1		T22	2
valid_sources[0x7b]	20900	1			T35	2		T38	4		T22	3
valid_sources[0x7c]	19898	1			T37	4		T38	1		T20	2
valid_sources[0x7d]	24997	1			T33	8		T35	3		T38	2
valid_sources[0x7e]	21760	1			T33	3		T35	1		T38	3
valid_sources[0x7f]	20250	1			T20	2		T22	5		T24	1
valid_sources[0x80]	21159	1			T33	3		T35	1		T38	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1586271

1

T33

56

T34

59

T35

32

values[0x0]

all_enables

biggest_size

1902273

1

T33

37

T34

59

T35

111

values[0x1]

all_enables

biggest_size

1903653

1

T33

43

T34

51

T35

127