Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	56608705	0	0	0
ctrl_en_input_filter_rd_A	56608705	65993	0	0
intr_ctrl_en_falling_rd_A	56608705	65221	0	0
intr_ctrl_en_lvlhigh_rd_A	56608705	65704	0	0
intr_ctrl_en_lvllow_rd_A	56608705	66461	0	0
intr_ctrl_en_rising_rd_A	56608705	65656	0	0
intr_enable_rd_A	56608705	65665	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56608705	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56608705	65993	0	0
T1	50522	327	0	0
T2	0	96	0	0
T3	0	329	0	0
T4	0	216	0	0
T5	0	31	0	0
T6	0	112	0	0
T7	0	574	0	0
T8	0	2244	0	0
T9	0	123	0	0
T10	0	1280	0	0
T11	9411	0	0	0
T12	1010	0	0	0
T13	2059	0	0	0
T14	4105	0	0	0
T15	2785	0	0	0
T16	2453	0	0	0
T17	2117	0	0	0
T18	2735	0	0	0
T19	10210	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56608705	65221	0	0
T1	0	303	0	0
T2	0	100	0	0
T3	0	375	0	0
T4	0	183	0	0
T5	0	40	0	0
T6	0	126	0	0
T7	0	815	0	0
T8	0	2043	0	0
T20	7593	8	0	0
T21	0	2	0	0
T22	12923	0	0	0
T23	19434	0	0	0
T24	7276	0	0	0
T25	3735	0	0	0
T26	1112	0	0	0
T27	8293	0	0	0
T28	3993	0	0	0
T29	6551	0	0	0
T30	4301	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56608705	65704	0	0
T1	0	344	0	0
T2	0	97	0	0
T3	0	368	0	0
T4	0	189	0	0
T5	0	30	0	0
T6	0	144	0	0
T7	0	578	0	0
T20	7593	1	0	0
T21	0	1	0	0
T22	12923	0	0	0
T23	19434	0	0	0
T24	7276	0	0	0
T25	3735	0	0	0
T26	1112	0	0	0
T27	8293	0	0	0
T28	3993	0	0	0
T29	6551	0	0	0
T30	4301	0	0	0
T31	0	3	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56608705	66461	0	0
T1	0	394	0	0
T2	0	92	0	0
T3	0	321	0	0
T4	0	172	0	0
T5	0	33	0	0
T6	0	180	0	0
T7	0	778	0	0
T8	0	2020	0	0
T20	7593	2	0	0
T22	12923	0	0	0
T23	19434	0	0	0
T24	7276	0	0	0
T25	3735	0	0	0
T26	1112	0	0	0
T27	8293	0	0	0
T28	3993	0	0	0
T29	6551	0	0	0
T30	4301	0	0	0
T31	0	1	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56608705	65656	0	0
T1	0	383	0	0
T2	0	81	0	0
T3	0	348	0	0
T4	0	223	0	0
T5	0	18	0	0
T6	0	136	0	0
T7	0	660	0	0
T8	0	2267	0	0
T20	7593	8	0	0
T22	12923	0	0	0
T23	19434	0	0	0
T24	7276	0	0	0
T25	3735	0	0	0
T26	1112	0	0	0
T27	8293	0	0	0
T28	3993	0	0	0
T29	6551	0	0	0
T30	4301	0	0	0
T32	0	8	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56608705	65665	0	0
T1	0	375	0	0
T2	0	85	0	0
T3	0	428	0	0
T4	0	206	0	0
T5	0	25	0	0
T6	0	120	0	0
T7	0	796	0	0
T20	7593	2	0	0
T21	0	7	0	0
T22	12923	0	0	0
T23	19434	0	0	0
T24	7276	0	0	0
T25	3735	0	0	0
T26	1112	0	0	0
T27	8293	0	0	0
T28	3993	0	0	0
T29	6551	0	0	0
T30	4301	0	0	0
T31	0	4	0	0