Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	1463377	1			T33	1		T34	1		T35	1
all_pins[1]	1463377	1			T33	1		T34	1		T35	1
all_pins[2]	1463377	1			T33	1		T34	1		T35	1
all_pins[3]	1463377	1			T33	1		T34	1		T35	1
all_pins[4]	1463377	1			T33	1		T34	1		T35	1
all_pins[5]	1463377	1			T33	1		T34	1		T35	1
all_pins[6]	1463377	1			T33	1		T34	1		T35	1
all_pins[7]	1463377	1			T33	1		T34	1		T35	1
all_pins[8]	1463377	1			T33	1		T34	1		T35	1
all_pins[9]	1463377	1			T33	1		T34	1		T35	1
all_pins[10]	1463377	1			T33	1		T34	1		T35	1
all_pins[11]	1463377	1			T33	1		T34	1		T35	1
all_pins[12]	1463377	1			T33	1		T34	1		T35	1
all_pins[13]	1463377	1			T33	1		T34	1		T35	1
all_pins[14]	1463377	1			T33	1		T34	1		T35	1
all_pins[15]	1463377	1			T33	1		T34	1		T35	1
all_pins[16]	1463377	1			T33	1		T34	1		T35	1
all_pins[17]	1463377	1			T33	1		T34	1		T35	1
all_pins[18]	1463377	1			T33	1		T34	1		T35	1
all_pins[19]	1463377	1			T33	1		T34	1		T35	1
all_pins[20]	1463377	1			T33	1		T34	1		T35	1
all_pins[21]	1463377	1			T33	1		T34	1		T35	1
all_pins[22]	1463377	1			T33	1		T34	1		T35	1
all_pins[23]	1463377	1			T33	1		T34	1		T35	1
all_pins[24]	1463377	1			T33	1		T34	1		T35	1
all_pins[25]	1463377	1			T33	1		T34	1		T35	1
all_pins[26]	1463377	1			T33	1		T34	1		T35	1
all_pins[27]	1463377	1			T33	1		T34	1		T35	1
all_pins[28]	1463377	1			T33	1		T34	1		T35	1
all_pins[29]	1463377	1			T33	1		T34	1		T35	1
all_pins[30]	1463377	1			T33	1		T34	1		T35	1
all_pins[31]	1463377	1			T33	1		T34	1		T35	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	29098607	1			T33	32		T34	32		T35	32
values[0x1]	17729457	1			T38	1196		T20	311		T21	10272
transitions[0x0=>0x1]	10610947	1			T38	706		T20	255		T21	6436
transitions[0x1=>0x0]	10610793	1			T38	706		T20	255		T21	6435

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	912017	1			T33	1		T34	1		T35	1
all_pins[0]	values[0x1]	551360	1			T38	32		T20	15		T21	276
all_pins[0]	transitions[0x0=>0x1]	341298	1			T38	18		T20	15		T21	155
all_pins[0]	transitions[0x1=>0x0]	345627	1			T38	18		T21	242		T22	118
all_pins[1]	values[0x0]	908288	1			T33	1		T34	1		T35	1
all_pins[1]	values[0x1]	555089	1			T38	35		T20	5		T21	271
all_pins[1]	transitions[0x0=>0x1]	332617	1			T38	22		T20	3		T21	173
all_pins[1]	transitions[0x1=>0x0]	328888	1			T38	19		T20	13		T21	178
all_pins[2]	values[0x0]	910608	1			T33	1		T34	1		T35	1
all_pins[2]	values[0x1]	552769	1			T38	26		T20	4		T21	346
all_pins[2]	transitions[0x0=>0x1]	330164	1			T38	17		T20	4		T21	230
all_pins[2]	transitions[0x1=>0x0]	332484	1			T38	26		T20	5		T21	155
all_pins[3]	values[0x0]	909947	1			T33	1		T34	1		T35	1
all_pins[3]	values[0x1]	553430	1			T38	39		T20	18		T21	323
all_pins[3]	transitions[0x0=>0x1]	332864	1			T38	32		T20	17		T21	211
all_pins[3]	transitions[0x1=>0x0]	332203	1			T38	19		T20	3		T21	234
all_pins[4]	values[0x0]	911364	1			T33	1		T34	1		T35	1
all_pins[4]	values[0x1]	552013	1			T38	31		T20	7		T21	235
all_pins[4]	transitions[0x0=>0x1]	328469	1			T38	14		T20	4		T21	175
all_pins[4]	transitions[0x1=>0x0]	329886	1			T38	22		T20	15		T21	263
all_pins[5]	values[0x0]	906072	1			T33	1		T34	1		T35	1
all_pins[5]	values[0x1]	557305	1			T38	34		T20	12		T21	245
all_pins[5]	transitions[0x0=>0x1]	334199	1			T38	24		T20	10		T21	197
all_pins[5]	transitions[0x1=>0x0]	328907	1			T38	21		T20	5		T21	187
all_pins[6]	values[0x0]	910519	1			T33	1		T34	1		T35	1
all_pins[6]	values[0x1]	552858	1			T38	42		T20	6		T21	403
all_pins[6]	transitions[0x0=>0x1]	330677	1			T38	28		T20	4		T21	288
all_pins[6]	transitions[0x1=>0x0]	335124	1			T38	20		T20	10		T21	130
all_pins[7]	values[0x0]	909376	1			T33	1		T34	1		T35	1
all_pins[7]	values[0x1]	554001	1			T38	38		T20	20		T21	301
all_pins[7]	transitions[0x0=>0x1]	331058	1			T38	24		T20	15		T21	163
all_pins[7]	transitions[0x1=>0x0]	329915	1			T38	28		T20	1		T21	265
all_pins[8]	values[0x0]	907192	1			T33	1		T34	1		T35	1
all_pins[8]	values[0x1]	556185	1			T38	30		T20	9		T21	265
all_pins[8]	transitions[0x0=>0x1]	332855	1			T38	12		T20	3		T21	190
all_pins[8]	transitions[0x1=>0x0]	330671	1			T38	20		T20	14		T21	226
all_pins[9]	values[0x0]	907334	1			T33	1		T34	1		T35	1
all_pins[9]	values[0x1]	556043	1			T38	42		T20	19		T21	356
all_pins[9]	transitions[0x0=>0x1]	332388	1			T38	33		T20	15		T21	259
all_pins[9]	transitions[0x1=>0x0]	332530	1			T38	21		T20	5		T21	168
all_pins[10]	values[0x0]	908381	1			T33	1		T34	1		T35	1
all_pins[10]	values[0x1]	554996	1			T38	36		T20	10		T21	327
all_pins[10]	transitions[0x0=>0x1]	330326	1			T38	27		T20	6		T21	174
all_pins[10]	transitions[0x1=>0x0]	331373	1			T38	33		T20	15		T21	203
all_pins[11]	values[0x0]	908591	1			T33	1		T34	1		T35	1
all_pins[11]	values[0x1]	554786	1			T38	43		T20	3		T21	361
all_pins[11]	transitions[0x0=>0x1]	329477	1			T38	28		T20	3		T21	235
all_pins[11]	transitions[0x1=>0x0]	329687	1			T38	21		T20	10		T21	201
all_pins[12]	values[0x0]	909773	1			T33	1		T34	1		T35	1
all_pins[12]	values[0x1]	553604	1			T38	33		T20	9		T21	315
all_pins[12]	transitions[0x0=>0x1]	331383	1			T38	8		T20	6		T21	179
all_pins[12]	transitions[0x1=>0x0]	332565	1			T38	18		T21	225		T22	119
all_pins[13]	values[0x0]	909305	1			T33	1		T34	1		T35	1
all_pins[13]	values[0x1]	554072	1			T38	37		T20	20		T21	425
all_pins[13]	transitions[0x0=>0x1]	332020	1			T38	25		T20	20		T21	305
all_pins[13]	transitions[0x1=>0x0]	331552	1			T38	21		T20	9		T21	195
all_pins[14]	values[0x0]	911278	1			T33	1		T34	1		T35	1
all_pins[14]	values[0x1]	552099	1			T38	28		T20	3		T21	285
all_pins[14]	transitions[0x0=>0x1]	330362	1			T38	16		T20	1		T21	106
all_pins[14]	transitions[0x1=>0x0]	332335	1			T38	25		T20	18		T21	246
all_pins[15]	values[0x0]	908567	1			T33	1		T34	1		T35	1
all_pins[15]	values[0x1]	554810	1			T38	44		T20	8		T21	335
all_pins[15]	transitions[0x0=>0x1]	330753	1			T38	30		T20	8		T21	227
all_pins[15]	transitions[0x1=>0x0]	328042	1			T38	14		T20	3		T21	177
all_pins[16]	values[0x0]	909512	1			T33	1		T34	1		T35	1
all_pins[16]	values[0x1]	553865	1			T38	30		T20	12		T21	374
all_pins[16]	transitions[0x0=>0x1]	332111	1			T38	10		T20	9		T21	211
all_pins[16]	transitions[0x1=>0x0]	333056	1			T38	24		T20	5		T21	172
all_pins[17]	values[0x0]	909992	1			T33	1		T34	1		T35	1
all_pins[17]	values[0x1]	553385	1			T38	57		T20	5		T21	399
all_pins[17]	transitions[0x0=>0x1]	332483	1			T38	34		T20	4		T21	190
all_pins[17]	transitions[0x1=>0x0]	332963	1			T38	7		T20	11		T21	165
all_pins[18]	values[0x0]	910355	1			T33	1		T34	1		T35	1
all_pins[18]	values[0x1]	553022	1			T38	38		T20	9		T21	468
all_pins[18]	transitions[0x0=>0x1]	329997	1			T38	17		T20	9		T21	242
all_pins[18]	transitions[0x1=>0x0]	330360	1			T38	36		T20	5		T21	173
all_pins[19]	values[0x0]	908329	1			T33	1		T34	1		T35	1
all_pins[19]	values[0x1]	555048	1			T38	33		T20	10		T21	266
all_pins[19]	transitions[0x0=>0x1]	331293	1			T38	21		T20	7		T21	135
all_pins[19]	transitions[0x1=>0x0]	329267	1			T38	26		T20	6		T21	337
all_pins[20]	values[0x0]	910976	1			T33	1		T34	1		T35	1
all_pins[20]	values[0x1]	552401	1			T38	45		T21	247		T22	135
all_pins[20]	transitions[0x0=>0x1]	329894	1			T38	29		T21	163		T22	82
all_pins[20]	transitions[0x1=>0x0]	332541	1			T38	17		T20	10		T21	182
all_pins[21]	values[0x0]	909027	1			T33	1		T34	1		T35	1
all_pins[21]	values[0x1]	554350	1			T38	16		T20	15		T21	334
all_pins[21]	transitions[0x0=>0x1]	331517	1			T38	8		T20	15		T21	198
all_pins[21]	transitions[0x1=>0x0]	329568	1			T38	37		T21	111		T22	103
all_pins[22]	values[0x0]	910499	1			T33	1		T34	1		T35	1
all_pins[22]	values[0x1]	552878	1			T38	26		T20	4		T21	321
all_pins[22]	transitions[0x0=>0x1]	329931	1			T38	25		T20	4		T21	210
all_pins[22]	transitions[0x1=>0x0]	331403	1			T38	15		T20	15		T21	223
all_pins[23]	values[0x0]	910364	1			T33	1		T34	1		T35	1
all_pins[23]	values[0x1]	553013	1			T38	60		T20	19		T21	212
all_pins[23]	transitions[0x0=>0x1]	331077	1			T38	47		T20	19		T21	146
all_pins[23]	transitions[0x1=>0x0]	330942	1			T38	13		T20	4		T21	255
all_pins[24]	values[0x0]	910864	1			T33	1		T34	1		T35	1
all_pins[24]	values[0x1]	552513	1			T38	41		T20	4		T21	242
all_pins[24]	transitions[0x0=>0x1]	329206	1			T38	20		T20	3		T21	182
all_pins[24]	transitions[0x1=>0x0]	329706	1			T38	39		T20	18		T21	152
all_pins[25]	values[0x0]	910172	1			T33	1		T34	1		T35	1
all_pins[25]	values[0x1]	553205	1			T38	51		T20	6		T21	423
all_pins[25]	transitions[0x0=>0x1]	330500	1			T38	28		T20	5		T21	289
all_pins[25]	transitions[0x1=>0x0]	329808	1			T38	18		T20	3		T21	108
all_pins[26]	values[0x0]	910368	1			T33	1		T34	1		T35	1
all_pins[26]	values[0x1]	553009	1			T38	39		T20	7		T21	229
all_pins[26]	transitions[0x0=>0x1]	332323	1			T38	20		T20	6		T21	111
all_pins[26]	transitions[0x1=>0x0]	332519	1			T38	32		T20	5		T21	305
all_pins[27]	values[0x0]	908325	1			T33	1		T34	1		T35	1
all_pins[27]	values[0x1]	555052	1			T38	30		T20	16		T21	310
all_pins[27]	transitions[0x0=>0x1]	332327	1			T38	14		T20	16		T21	253
all_pins[27]	transitions[0x1=>0x0]	330284	1			T38	23		T20	7		T21	172
all_pins[28]	values[0x0]	907971	1			T33	1		T34	1		T35	1
all_pins[28]	values[0x1]	555406	1			T38	46		T20	9		T21	304
all_pins[28]	transitions[0x0=>0x1]	331780	1			T38	27		T20	9		T21	174
all_pins[28]	transitions[0x1=>0x0]	331426	1			T38	11		T20	16		T21	180
all_pins[29]	values[0x0]	907969	1			T33	1		T34	1		T35	1
all_pins[29]	values[0x1]	555408	1			T38	31		T20	7		T21	439
all_pins[29]	transitions[0x0=>0x1]	331851	1			T38	7		T20	1		T21	291
all_pins[29]	transitions[0x1=>0x0]	331849	1			T38	22		T20	3		T21	156
all_pins[30]	values[0x0]	907738	1			T33	1		T34	1		T35	1
all_pins[30]	values[0x1]	555639	1			T38	51		T20	20		T21	271
all_pins[30]	transitions[0x0=>0x1]	331569	1			T38	33		T20	14		T21	112
all_pins[30]	transitions[0x1=>0x0]	331338	1			T38	13		T20	1		T21	280
all_pins[31]	values[0x0]	907534	1			T33	1		T34	1		T35	1
all_pins[31]	values[0x1]	555843	1			T38	32		T21	364		T22	183
all_pins[31]	transitions[0x0=>0x1]	332178	1			T38	8		T21	262		T22	119
all_pins[31]	transitions[0x1=>0x0]	331974	1			T38	27		T20	20		T21	169