Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[1]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[2]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[3]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[4]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[5]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[6]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[7]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[8]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[9]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[10]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[11]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[12]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[13]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[14]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[15]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[16]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[17]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[18]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[19]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[20]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[21]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[22]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[23]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[24]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[25]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[26]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[27]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[28]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[29]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[30]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[31]	6396882	1			T33	869		T34	584		T35	768

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

103188860

1

T33

19788

T34

12970

T35

19482

auto[1]

101511364

1

T33

8020

T34

5718

T35

5094

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

172081984

1

T33

16066

T34

11682

T35

18713

auto[1]

32618240

1

T33

11742

T34

7006

T35

5863

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

163063486

1

T33

16328

T34

11790

T35

12455

auto[1]

41636738

1

T33

11480

T34

6898

T35

12121

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	2303770	1			T33	231		T34	179		T35	321
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	2277836	1			T33	73		T34	75		T35	33
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	518938	1			T33	209		T34	123		T35	96
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	407106	1			T33	160		T34	109		T35	217
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	385919	1			T35	27		T36	110		T37	25
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	503313	1			T33	196		T34	98		T35	74
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	2300856	1			T33	286		T34	159		T35	259
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	2279135	1			T33	59		T34	76		T35	44
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	510787	1			T33	196		T34	90		T35	101
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	407403	1			T33	168		T34	117		T35	240
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	386724	1			T35	23		T36	32		T37	24
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	511977	1			T33	160		T34	142		T35	101
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	2307277	1			T33	280		T34	205		T35	243
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	2279717	1			T33	72		T34	70		T35	27
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	509972	1			T33	122		T34	110		T35	98
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	408260	1			T33	212		T34	118		T35	270
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	385620	1			T35	34		T36	143		T37	16
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	506036	1			T33	183		T34	81		T35	96
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	2298017	1			T33	277		T34	181		T35	249
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	2277854	1			T33	67		T34	67		T35	35
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	513446	1			T33	210		T34	117		T35	78
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	408593	1			T33	152		T34	91		T35	312
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	388776	1			T35	34		T36	103		T37	16
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	510196	1			T33	163		T34	128		T35	60
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	2317712	1			T33	225		T34	207		T35	252
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	2265605	1			T33	71		T34	77		T35	43
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	513382	1			T33	209		T34	89		T35	82
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	407882	1			T33	152		T34	103		T35	243
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	384222	1			T35	31		T36	135		T37	34
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	508079	1			T33	212		T34	108		T35	117
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	2305511	1			T33	218		T34	207		T35	280
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	2282410	1			T33	74		T34	68		T35	25
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	515095	1			T33	157		T34	90		T35	96
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	407300	1			T33	192		T34	137		T35	244
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	382140	1			T35	29		T36	85		T37	18
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	504426	1			T33	228		T34	82		T35	94
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	2308476	1			T33	268		T34	205		T35	211
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	2274302	1			T33	61		T34	66		T35	34
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	513772	1			T33	184		T34	118		T35	49
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	407412	1			T33	200		T34	112		T35	340
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	384254	1			T35	32		T36	134		T37	15
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	508666	1			T33	156		T34	83		T35	102
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	2296988	1			T33	240		T34	186		T35	276
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	2282798	1			T33	67		T34	74		T35	40
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	513000	1			T33	190		T34	106		T35	121
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	408513	1			T33	182		T34	133		T35	193
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	383198	1			T35	33		T36	109		T37	27
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	512385	1			T33	190		T34	85		T35	105
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	2304245	1			T33	267		T34	173		T35	193
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	2272119	1			T33	74		T34	71		T35	23
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	514403	1			T33	180		T34	102		T35	43
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	407440	1			T33	160		T34	131		T35	309
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	387680	1			T35	47		T36	72		T37	17
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	510995	1			T33	188		T34	107		T35	153
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	2300730	1			T33	218		T34	192		T35	196
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	2284526	1			T33	72		T34	75		T35	38
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	513960	1			T33	195		T34	114		T35	98
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	407196	1			T33	194		T34	109		T35	270
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	384829	1			T35	44		T36	107		T37	17
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	505641	1			T33	190		T34	94		T35	122
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	2303960	1			T33	266		T34	177		T35	277
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	2278064	1			T33	72		T34	67		T35	21
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	511112	1			T33	208		T34	106		T35	69
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	407816	1			T33	134		T34	100		T35	279
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	386974	1			T35	43		T36	37		T37	27
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	508956	1			T33	189		T34	134		T35	79
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	2299776	1			T33	263		T34	169		T35	207
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	2282308	1			T33	72		T34	85		T35	34
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	514128	1			T33	154		T34	100		T35	85
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	406365	1			T33	198		T34	109		T35	277
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	386617	1			T35	32		T36	80		T37	16
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	507688	1			T33	182		T34	121		T35	133
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	2307152	1			T33	264		T34	183		T35	257
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	2279205	1			T33	66		T34	63		T35	35
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	511485	1			T33	184		T34	144		T35	90
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	407456	1			T33	174		T34	86		T35	284
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	385565	1			T35	30		T36	72		T37	10
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	506019	1			T33	181		T34	108		T35	72
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	2300646	1			T33	237		T34	169		T35	255
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	2277725	1			T33	69		T34	72		T35	34
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	515519	1			T33	208		T34	108		T35	134
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	410616	1			T33	183		T34	123		T35	236
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	383401	1			T35	30		T36	71		T37	18
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	508975	1			T33	172		T34	112		T35	79
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	2299414	1			T33	260		T34	189		T35	282
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	2284053	1			T33	68		T34	66		T35	38
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	513810	1			T33	205		T34	125		T35	83
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	408835	1			T33	160		T34	110		T35	239
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	385612	1			T35	29		T36	73		T37	36
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	505158	1			T33	176		T34	94		T35	97
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	2298783	1			T33	230		T34	174		T35	217
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	2280311	1			T33	76		T34	82		T35	38
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	513267	1			T33	223		T34	110		T35	126
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	410054	1			T33	178		T34	103		T35	244
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	389016	1			T35	40		T36	64		T37	19
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	505451	1			T33	162		T34	115		T35	103
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	2319160	1			T33	249		T34	211		T35	269
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	2263675	1			T33	69		T34	72		T35	38
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	510939	1			T33	176		T34	93		T35	94
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	410334	1			T33	171		T34	104		T35	224
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	386742	1			T35	34		T36	58		T37	34
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	506032	1			T33	204		T34	104		T35	109
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	2301108	1			T33	263		T34	184		T35	271
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	2282281	1			T33	64		T34	74		T35	29
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	511693	1			T33	202		T34	143		T35	78
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	408538	1			T33	170		T34	66		T35	258
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	386266	1			T35	34		T36	155		T37	19
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	506996	1			T33	170		T34	117		T35	98
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	2293052	1			T33	225		T34	175		T35	260
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	2290951	1			T33	75		T34	74		T35	40
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	511671	1			T33	190		T34	127		T35	111
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	408078	1			T33	192		T34	86		T35	255
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	387931	1			T35	26		T36	67		T37	35
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	505199	1			T33	187		T34	122		T35	76
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	2300409	1			T33	269		T34	181		T35	336
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	2287261	1			T33	69		T34	86		T35	36
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	509588	1			T33	188		T34	110		T35	116
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	407508	1			T33	166		T34	113		T35	210
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	386022	1			T35	21		T36	98		T37	12
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	506094	1			T33	177		T34	94		T35	49
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	2311157	1			T33	264		T34	200		T35	256
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	2273243	1			T33	78		T34	70		T35	35
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	511190	1			T33	180		T34	88		T35	98
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	407316	1			T33	175		T34	107		T35	242
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	385322	1			T35	37		T36	79		T37	17
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	508654	1			T33	172		T34	119		T35	100
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	2301354	1			T33	271		T34	180		T35	260
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	2280864	1			T33	61		T34	73		T35	23
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	510959	1			T33	190		T34	84		T35	83
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	408169	1			T33	160		T34	114		T35	295
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	389838	1			T35	39		T36	92		T37	30
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	505698	1			T33	187		T34	133		T35	68
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	2308674	1			T33	245		T34	163		T35	302
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	2279381	1			T33	75		T34	71		T35	37
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	511324	1			T33	153		T34	115		T35	74
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	408201	1			T33	224		T34	118		T35	225
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	382900	1			T35	34		T36	124		T37	15
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	506402	1			T33	172		T34	117		T35	96
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	2311503	1			T33	264		T34	175		T35	297
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	2276580	1			T33	68		T34	58		T35	40
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	513010	1			T33	165		T34	131		T35	118
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	406238	1			T33	204		T34	116		T35	256
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	384398	1			T35	25		T36	61		T37	17
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	505153	1			T33	168		T34	104		T35	32
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	2297252	1			T33	257		T34	174		T35	318
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	2286235	1			T33	69		T34	72		T35	47
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	512138	1			T33	216		T34	114		T35	98
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	408920	1			T33	162		T34	98		T35	191
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	386569	1			T35	33		T36	90		T37	19
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	505768	1			T33	165		T34	126		T35	81
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	2301902	1			T33	288		T34	197		T35	276
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	2282738	1			T33	58		T34	69		T35	38
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	513338	1			T33	188		T34	111		T35	95
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	408201	1			T33	163		T34	118		T35	240
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	387637	1			T35	36		T36	69		T37	29
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	503066	1			T33	172		T34	89		T35	83
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	2302024	1			T33	224		T34	167		T35	297
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	2278099	1			T33	74		T34	76		T35	45
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	511071	1			T33	195		T34	134		T35	116
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	408447	1			T33	210		T34	93		T35	216
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	388412	1			T35	23		T36	136		T37	27
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	508829	1			T33	166		T34	114		T35	71
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	2309564	1			T33	252		T34	174		T35	284
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	2274864	1			T33	60		T34	78		T35	28
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	513736	1			T33	226		T34	132		T35	83
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	408750	1			T33	156		T34	96		T35	230
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	385462	1			T35	38		T36	114		T37	23
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	504506	1			T33	175		T34	104		T35	105
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	2308682	1			T33	232		T34	198		T35	244
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	2276945	1			T33	77		T34	69		T35	32
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	512098	1			T33	160		T34	142		T35	103
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	408202	1			T33	172		T34	101		T35	252
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	386624	1			T35	39		T36	84		T37	23
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	504331	1			T33	228		T34	74		T35	98
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	2297480	1			T33	295		T34	168		T35	230
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	2287293	1			T33	77		T34	76		T35	32
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	510463	1			T33	150		T34	89		T35	89
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	410274	1			T33	157		T34	120		T35	280
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	385065	1			T35	40		T36	120		T37	37
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	506307	1			T33	190		T34	131		T35	97
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	2306908	1			T33	271		T34	176		T35	237
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	2279876	1			T33	67		T34	68		T35	38
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	510111	1			T33	184		T34	114		T35	72
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	408953	1			T33	187		T34	116		T35	304
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	386818	1			T35	25		T36	67		T37	30
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	504216	1			T33	160		T34	110		T35	92
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	2298757	1			T33	265		T34	222		T35	262
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	2282404	1			T33	67		T34	61		T35	50
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	511124	1			T33	146		T34	110		T35	74
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	411656	1			T33	213		T34	124		T35	282
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	386442	1			T35	30		T36	78		T37	22
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	506499	1			T33	178		T34	67		T35	70

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal