Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[1]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[2]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[3]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[4]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[5]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[6]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[7]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[8]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[9]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[10]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[11]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[12]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[13]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[14]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[15]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[16]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[17]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[18]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[19]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[20]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[21]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[22]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[23]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[24]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[25]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[26]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[27]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[28]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[29]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[30]	6396882	1			T33	869		T34	584		T35	768
bins_for_gpio_bits[31]	6396882	1			T33	869		T34	584		T35	768

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

103188860

1

T33

19788

T34

12970

T35

19482

auto[1]

101511364

1

T33

8020

T34

5718

T35

5094

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

103182862

1

T33

19779

T34

12961

T35

19482

auto[1]

101517362

1

T33

8029

T34

5727

T35

5094

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	3138098	1			T33	565		T34	379		T35	620
bins_for_gpio_bits[0]	auto[0]	auto[1]	91580	1			T33	35		T34	32		T35	14
bins_for_gpio_bits[0]	auto[1]	auto[0]	91716	1			T33	35		T34	32		T35	14
bins_for_gpio_bits[0]	auto[1]	auto[1]	3075488	1			T33	234		T34	141		T35	120
bins_for_gpio_bits[1]	auto[0]	auto[0]	3127206	1			T33	604		T34	332		T35	579
bins_for_gpio_bits[1]	auto[0]	auto[1]	91679	1			T33	46		T34	34		T35	21
bins_for_gpio_bits[1]	auto[1]	auto[0]	91840	1			T33	46		T34	34		T35	21
bins_for_gpio_bits[1]	auto[1]	auto[1]	3086157	1			T33	173		T34	184		T35	147
bins_for_gpio_bits[2]	auto[0]	auto[0]	3134170	1			T33	566		T34	413		T35	597
bins_for_gpio_bits[2]	auto[0]	auto[1]	91153	1			T33	47		T34	20		T35	14
bins_for_gpio_bits[2]	auto[1]	auto[0]	91339	1			T33	48		T34	20		T35	14
bins_for_gpio_bits[2]	auto[1]	auto[1]	3080220	1			T33	208		T34	131		T35	143
bins_for_gpio_bits[3]	auto[0]	auto[0]	3128658	1			T33	597		T34	359		T35	624
bins_for_gpio_bits[3]	auto[0]	auto[1]	91262	1			T33	41		T34	30		T35	15
bins_for_gpio_bits[3]	auto[1]	auto[0]	91398	1			T33	42		T34	30		T35	15
bins_for_gpio_bits[3]	auto[1]	auto[1]	3085564	1			T33	189		T34	165		T35	114
bins_for_gpio_bits[4]	auto[0]	auto[0]	3147191	1			T33	534		T34	378		T35	558
bins_for_gpio_bits[4]	auto[0]	auto[1]	91623	1			T33	52		T34	21		T35	19
bins_for_gpio_bits[4]	auto[1]	auto[0]	91785	1			T33	52		T34	21		T35	19
bins_for_gpio_bits[4]	auto[1]	auto[1]	3066283	1			T33	231		T34	164		T35	172
bins_for_gpio_bits[5]	auto[0]	auto[0]	3136030	1			T33	513		T34	413		T35	601
bins_for_gpio_bits[5]	auto[0]	auto[1]	91706	1			T33	54		T34	21		T35	19
bins_for_gpio_bits[5]	auto[1]	auto[0]	91876	1			T33	54		T34	21		T35	19
bins_for_gpio_bits[5]	auto[1]	auto[1]	3077270	1			T33	248		T34	129		T35	129
bins_for_gpio_bits[6]	auto[0]	auto[0]	3137641	1			T33	609		T34	411		T35	579
bins_for_gpio_bits[6]	auto[0]	auto[1]	91805	1			T33	43		T34	23		T35	21
bins_for_gpio_bits[6]	auto[1]	auto[0]	92019	1			T33	43		T34	24		T35	21
bins_for_gpio_bits[6]	auto[1]	auto[1]	3075417	1			T33	174		T34	126		T35	147
bins_for_gpio_bits[7]	auto[0]	auto[0]	3126571	1			T33	567		T34	403		T35	574
bins_for_gpio_bits[7]	auto[0]	auto[1]	91716	1			T33	45		T34	22		T35	16
bins_for_gpio_bits[7]	auto[1]	auto[0]	91930	1			T33	45		T34	22		T35	16
bins_for_gpio_bits[7]	auto[1]	auto[1]	3086665	1			T33	212		T34	137		T35	162
bins_for_gpio_bits[8]	auto[0]	auto[0]	3133587	1			T33	563		T34	374		T35	521
bins_for_gpio_bits[8]	auto[0]	auto[1]	92318	1			T33	44		T34	31		T35	24
bins_for_gpio_bits[8]	auto[1]	auto[0]	92501	1			T33	44		T34	32		T35	24
bins_for_gpio_bits[8]	auto[1]	auto[1]	3078476	1			T33	218		T34	147		T35	199
bins_for_gpio_bits[9]	auto[0]	auto[0]	3129936	1			T33	560		T34	386		T35	543
bins_for_gpio_bits[9]	auto[0]	auto[1]	91752	1			T33	47		T34	29		T35	21
bins_for_gpio_bits[9]	auto[1]	auto[0]	91950	1			T33	47		T34	29		T35	21
bins_for_gpio_bits[9]	auto[1]	auto[1]	3083244	1			T33	215		T34	140		T35	183
bins_for_gpio_bits[10]	auto[0]	auto[0]	3130944	1			T33	561		T34	353		T35	607
bins_for_gpio_bits[10]	auto[0]	auto[1]	91747	1			T33	46		T34	30		T35	18
bins_for_gpio_bits[10]	auto[1]	auto[0]	91944	1			T33	47		T34	30		T35	18
bins_for_gpio_bits[10]	auto[1]	auto[1]	3082247	1			T33	215		T34	171		T35	125
bins_for_gpio_bits[11]	auto[0]	auto[0]	3128739	1			T33	568		T34	351		T35	545
bins_for_gpio_bits[11]	auto[0]	auto[1]	91362	1			T33	47		T34	26		T35	24
bins_for_gpio_bits[11]	auto[1]	auto[0]	91530	1			T33	47		T34	27		T35	24
bins_for_gpio_bits[11]	auto[1]	auto[1]	3085251	1			T33	207		T34	180		T35	175
bins_for_gpio_bits[12]	auto[0]	auto[0]	3134654	1			T33	579		T34	386		T35	613
bins_for_gpio_bits[12]	auto[0]	auto[1]	91252	1			T33	42		T34	27		T35	18
bins_for_gpio_bits[12]	auto[1]	auto[0]	91439	1			T33	43		T34	27		T35	18
bins_for_gpio_bits[12]	auto[1]	auto[1]	3079537	1			T33	205		T34	144		T35	119
bins_for_gpio_bits[13]	auto[0]	auto[0]	3135050	1			T33	584		T34	372		T35	611
bins_for_gpio_bits[13]	auto[0]	auto[1]	91539	1			T33	44		T34	28		T35	14
bins_for_gpio_bits[13]	auto[1]	auto[0]	91731	1			T33	44		T34	28		T35	14
bins_for_gpio_bits[13]	auto[1]	auto[1]	3078562	1			T33	197		T34	156		T35	129
bins_for_gpio_bits[14]	auto[0]	auto[0]	3130534	1			T33	579		T34	394		T35	586
bins_for_gpio_bits[14]	auto[0]	auto[1]	91304	1			T33	46		T34	30		T35	18
bins_for_gpio_bits[14]	auto[1]	auto[0]	91525	1			T33	46		T34	30		T35	18
bins_for_gpio_bits[14]	auto[1]	auto[1]	3083519	1			T33	198		T34	130		T35	146
bins_for_gpio_bits[15]	auto[0]	auto[0]	3130522	1			T33	591		T34	356		T35	568
bins_for_gpio_bits[15]	auto[0]	auto[1]	91394	1			T33	40		T34	30		T35	19
bins_for_gpio_bits[15]	auto[1]	auto[0]	91582	1			T33	40		T34	31		T35	19
bins_for_gpio_bits[15]	auto[1]	auto[1]	3083384	1			T33	198		T34	167		T35	162
bins_for_gpio_bits[16]	auto[0]	auto[0]	3148422	1			T33	545		T34	383		T35	568
bins_for_gpio_bits[16]	auto[0]	auto[1]	91851	1			T33	51		T34	25		T35	19
bins_for_gpio_bits[16]	auto[1]	auto[0]	92011	1			T33	51		T34	25		T35	19
bins_for_gpio_bits[16]	auto[1]	auto[1]	3064598	1			T33	222		T34	151		T35	162
bins_for_gpio_bits[17]	auto[0]	auto[0]	3129426	1			T33	594		T34	366		T35	590
bins_for_gpio_bits[17]	auto[0]	auto[1]	91712	1			T33	41		T34	26		T35	17
bins_for_gpio_bits[17]	auto[1]	auto[0]	91913	1			T33	41		T34	27		T35	17
bins_for_gpio_bits[17]	auto[1]	auto[1]	3083831	1			T33	193		T34	165		T35	144
bins_for_gpio_bits[18]	auto[0]	auto[0]	3120973	1			T33	562		T34	357		T35	612
bins_for_gpio_bits[18]	auto[0]	auto[1]	91593	1			T33	44		T34	31		T35	14
bins_for_gpio_bits[18]	auto[1]	auto[0]	91828	1			T33	45		T34	31		T35	14
bins_for_gpio_bits[18]	auto[1]	auto[1]	3092488	1			T33	218		T34	165		T35	128
bins_for_gpio_bits[19]	auto[0]	auto[0]	3125487	1			T33	576		T34	381		T35	651
bins_for_gpio_bits[19]	auto[0]	auto[1]	91825	1			T33	46		T34	23		T35	11
bins_for_gpio_bits[19]	auto[1]	auto[0]	92018	1			T33	47		T34	23		T35	11
bins_for_gpio_bits[19]	auto[1]	auto[1]	3087552	1			T33	200		T34	157		T35	95
bins_for_gpio_bits[20]	auto[0]	auto[0]	3137475	1			T33	569		T34	369		T35	582
bins_for_gpio_bits[20]	auto[0]	auto[1]	92021	1			T33	50		T34	26		T35	14
bins_for_gpio_bits[20]	auto[1]	auto[0]	92188	1			T33	50		T34	26		T35	14
bins_for_gpio_bits[20]	auto[1]	auto[1]	3075198	1			T33	200		T34	163		T35	158
bins_for_gpio_bits[21]	auto[0]	auto[0]	3128772	1			T33	570		T34	348		T35	624
bins_for_gpio_bits[21]	auto[0]	auto[1]	91461	1			T33	50		T34	29		T35	14
bins_for_gpio_bits[21]	auto[1]	auto[0]	91710	1			T33	51		T34	30		T35	14
bins_for_gpio_bits[21]	auto[1]	auto[1]	3084939	1			T33	198		T34	177		T35	116
bins_for_gpio_bits[22]	auto[0]	auto[0]	3136148	1			T33	580		T34	363		T35	587
bins_for_gpio_bits[22]	auto[0]	auto[1]	91897	1			T33	42		T34	33		T35	14
bins_for_gpio_bits[22]	auto[1]	auto[0]	92051	1			T33	42		T34	33		T35	14
bins_for_gpio_bits[22]	auto[1]	auto[1]	3076786	1			T33	205		T34	155		T35	153
bins_for_gpio_bits[23]	auto[0]	auto[0]	3138848	1			T33	591		T34	391		T35	662
bins_for_gpio_bits[23]	auto[0]	auto[1]	91694	1			T33	42		T34	31		T35	9
bins_for_gpio_bits[23]	auto[1]	auto[0]	91903	1			T33	42		T34	31		T35	9
bins_for_gpio_bits[23]	auto[1]	auto[1]	3074437	1			T33	194		T34	131		T35	88
bins_for_gpio_bits[24]	auto[0]	auto[0]	3126555	1			T33	589		T34	360		T35	591
bins_for_gpio_bits[24]	auto[0]	auto[1]	91585	1			T33	45		T34	26		T35	16
bins_for_gpio_bits[24]	auto[1]	auto[0]	91755	1			T33	46		T34	26		T35	16
bins_for_gpio_bits[24]	auto[1]	auto[1]	3086987	1			T33	189		T34	172		T35	145
bins_for_gpio_bits[25]	auto[0]	auto[0]	3131391	1			T33	597		T34	398		T35	595
bins_for_gpio_bits[25]	auto[0]	auto[1]	91896	1			T33	42		T34	27		T35	16
bins_for_gpio_bits[25]	auto[1]	auto[0]	92050	1			T33	42		T34	28		T35	16
bins_for_gpio_bits[25]	auto[1]	auto[1]	3081545	1			T33	188		T34	131		T35	141
bins_for_gpio_bits[26]	auto[0]	auto[0]	3129533	1			T33	587		T34	367		T35	613
bins_for_gpio_bits[26]	auto[0]	auto[1]	91820	1			T33	42		T34	27		T35	16
bins_for_gpio_bits[26]	auto[1]	auto[0]	92009	1			T33	42		T34	27		T35	16
bins_for_gpio_bits[26]	auto[1]	auto[1]	3083520	1			T33	198		T34	163		T35	123
bins_for_gpio_bits[27]	auto[0]	auto[0]	3140201	1			T33	593		T34	374		T35	577
bins_for_gpio_bits[27]	auto[0]	auto[1]	91621	1			T33	40		T34	28		T35	20
bins_for_gpio_bits[27]	auto[1]	auto[0]	91849	1			T33	41		T34	28		T35	20
bins_for_gpio_bits[27]	auto[1]	auto[1]	3073211	1			T33	195		T34	154		T35	151
bins_for_gpio_bits[28]	auto[0]	auto[0]	3137066	1			T33	514		T34	416		T35	581
bins_for_gpio_bits[28]	auto[0]	auto[1]	91713	1			T33	50		T34	25		T35	18
bins_for_gpio_bits[28]	auto[1]	auto[0]	91916	1			T33	50		T34	25		T35	18
bins_for_gpio_bits[28]	auto[1]	auto[1]	3076187	1			T33	255		T34	118		T35	151
bins_for_gpio_bits[29]	auto[0]	auto[0]	3126389	1			T33	558		T34	347		T35	580
bins_for_gpio_bits[29]	auto[0]	auto[1]	91628	1			T33	44		T34	30		T35	19
bins_for_gpio_bits[29]	auto[1]	auto[0]	91828	1			T33	44		T34	30		T35	19
bins_for_gpio_bits[29]	auto[1]	auto[1]	3087037	1			T33	223		T34	177		T35	150
bins_for_gpio_bits[30]	auto[0]	auto[0]	3133954	1			T33	600		T34	381		T35	599
bins_for_gpio_bits[30]	auto[0]	auto[1]	91817	1			T33	42		T34	24		T35	14
bins_for_gpio_bits[30]	auto[1]	auto[0]	92018	1			T33	42		T34	25		T35	14
bins_for_gpio_bits[30]	auto[1]	auto[1]	3079093	1			T33	185		T34	154		T35	141
bins_for_gpio_bits[31]	auto[0]	auto[0]	3129653	1			T33	575		T34	432		T35	603
bins_for_gpio_bits[31]	auto[0]	auto[1]	91712	1			T33	49		T34	23		T35	15
bins_for_gpio_bits[31]	auto[1]	auto[0]	91884	1			T33	49		T34	24		T35	15
bins_for_gpio_bits[31]	auto[1]	auto[1]	3083633	1			T33	196		T34	105		T35	135