Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4458075 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
| auto[1] |
1989558 |
1 |
|
|
T38 |
68 |
|
T20 |
29 |
|
T21 |
647 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6195787 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
| auto[1] |
251846 |
1 |
|
|
T38 |
4 |
|
T20 |
1 |
|
T21 |
164 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4446578 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
| auto[1] |
2001055 |
1 |
|
|
T38 |
75 |
|
T20 |
11 |
|
T21 |
845 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
884049 |
1 |
|
|
T38 |
45 |
|
T20 |
10 |
|
T21 |
449 |
| auto[1] |
auto[0] |
auto[1] |
127031 |
1 |
|
|
T38 |
3 |
|
T20 |
1 |
|
T21 |
110 |
| auto[1] |
auto[1] |
auto[0] |
865160 |
1 |
|
|
T38 |
26 |
|
T21 |
232 |
|
T22 |
128 |
| auto[1] |
auto[1] |
auto[1] |
124815 |
1 |
|
|
T38 |
1 |
|
T21 |
54 |
|
T22 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |