Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4430449 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
| auto[1] |
2017184 |
1 |
|
|
T38 |
72 |
|
T20 |
36 |
|
T21 |
723 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6193376 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
| auto[1] |
254257 |
1 |
|
|
T38 |
6 |
|
T21 |
187 |
|
T22 |
15 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4429023 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
| auto[1] |
2018610 |
1 |
|
|
T38 |
91 |
|
T20 |
14 |
|
T21 |
1031 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
881543 |
1 |
|
|
T38 |
53 |
|
T20 |
4 |
|
T21 |
561 |
| auto[1] |
auto[0] |
auto[1] |
126989 |
1 |
|
|
T38 |
4 |
|
T21 |
122 |
|
T22 |
5 |
| auto[1] |
auto[1] |
auto[0] |
882810 |
1 |
|
|
T38 |
32 |
|
T20 |
10 |
|
T21 |
283 |
| auto[1] |
auto[1] |
auto[1] |
127268 |
1 |
|
|
T38 |
2 |
|
T21 |
65 |
|
T22 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |