Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4434629 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
| auto[1] |
2013004 |
1 |
|
|
T38 |
74 |
|
T20 |
30 |
|
T21 |
925 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5456627 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
| auto[1] |
991006 |
1 |
|
|
T38 |
37 |
|
T20 |
8 |
|
T21 |
563 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4442517 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
| auto[1] |
2005116 |
1 |
|
|
T38 |
89 |
|
T20 |
24 |
|
T21 |
1124 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
507764 |
1 |
|
|
T38 |
40 |
|
T20 |
11 |
|
T21 |
261 |
| auto[1] |
auto[0] |
auto[1] |
496247 |
1 |
|
|
T38 |
30 |
|
T20 |
5 |
|
T21 |
285 |
| auto[1] |
auto[1] |
auto[0] |
506346 |
1 |
|
|
T38 |
12 |
|
T20 |
5 |
|
T21 |
300 |
| auto[1] |
auto[1] |
auto[1] |
494759 |
1 |
|
|
T38 |
7 |
|
T20 |
3 |
|
T21 |
278 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |