Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4430783 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
| auto[1] |
2016850 |
1 |
|
|
T38 |
111 |
|
T20 |
26 |
|
T21 |
1040 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5443178 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
| auto[1] |
1004455 |
1 |
|
|
T38 |
27 |
|
T20 |
1 |
|
T21 |
478 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4415742 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
| auto[1] |
2031891 |
1 |
|
|
T38 |
81 |
|
T20 |
10 |
|
T21 |
876 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
518535 |
1 |
|
|
T38 |
7 |
|
T20 |
3 |
|
T21 |
169 |
| auto[1] |
auto[0] |
auto[1] |
503393 |
1 |
|
|
T38 |
13 |
|
T20 |
1 |
|
T21 |
202 |
| auto[1] |
auto[1] |
auto[0] |
508901 |
1 |
|
|
T38 |
47 |
|
T20 |
6 |
|
T21 |
229 |
| auto[1] |
auto[1] |
auto[1] |
501062 |
1 |
|
|
T38 |
14 |
|
T21 |
276 |
|
T22 |
82 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |