Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4437253 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
| auto[1] |
2010380 |
1 |
|
|
T38 |
100 |
|
T20 |
39 |
|
T21 |
770 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6192983 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
| auto[1] |
254650 |
1 |
|
|
T38 |
6 |
|
T20 |
2 |
|
T21 |
248 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4426863 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
| auto[1] |
2020770 |
1 |
|
|
T38 |
75 |
|
T20 |
27 |
|
T21 |
1346 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
884437 |
1 |
|
|
T38 |
29 |
|
T20 |
10 |
|
T21 |
582 |
| auto[1] |
auto[0] |
auto[1] |
127769 |
1 |
|
|
T38 |
2 |
|
T20 |
1 |
|
T21 |
136 |
| auto[1] |
auto[1] |
auto[0] |
881683 |
1 |
|
|
T38 |
40 |
|
T20 |
15 |
|
T21 |
516 |
| auto[1] |
auto[1] |
auto[1] |
126881 |
1 |
|
|
T38 |
4 |
|
T20 |
1 |
|
T21 |
112 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |