Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4433845 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
auto[1] |
2013788 |
1 |
|
|
T38 |
71 |
|
T20 |
26 |
|
T21 |
676 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6196017 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
auto[1] |
251616 |
1 |
|
|
T38 |
9 |
|
T20 |
1 |
|
T21 |
135 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4447315 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
auto[1] |
2000318 |
1 |
|
|
T38 |
124 |
|
T20 |
25 |
|
T21 |
771 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
873141 |
1 |
|
|
T38 |
66 |
|
T20 |
11 |
|
T21 |
415 |
auto[1] |
auto[0] |
auto[1] |
124892 |
1 |
|
|
T38 |
6 |
|
T20 |
1 |
|
T21 |
86 |
auto[1] |
auto[1] |
auto[0] |
875561 |
1 |
|
|
T38 |
49 |
|
T20 |
13 |
|
T21 |
221 |
auto[1] |
auto[1] |
auto[1] |
126724 |
1 |
|
|
T38 |
3 |
|
T21 |
49 |
|
T22 |
19 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4437489 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
auto[1] |
2010144 |
1 |
|
|
T38 |
59 |
|
T20 |
47 |
|
T21 |
910 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6192831 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
auto[1] |
254802 |
1 |
|
|
T38 |
6 |
|
T20 |
1 |
|
T21 |
190 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4428576 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
auto[1] |
2019057 |
1 |
|
|
T38 |
79 |
|
T20 |
28 |
|
T21 |
1053 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
883205 |
1 |
|
|
T38 |
43 |
|
T20 |
8 |
|
T21 |
492 |
auto[1] |
auto[0] |
auto[1] |
127774 |
1 |
|
|
T38 |
4 |
|
T20 |
1 |
|
T21 |
106 |
auto[1] |
auto[1] |
auto[0] |
881050 |
1 |
|
|
T38 |
30 |
|
T20 |
19 |
|
T21 |
371 |
auto[1] |
auto[1] |
auto[1] |
127028 |
1 |
|
|
T38 |
2 |
|
T21 |
84 |
|
T22 |
14 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4442223 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
auto[1] |
2005410 |
1 |
|
|
T38 |
118 |
|
T20 |
11 |
|
T21 |
853 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6193716 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
auto[1] |
253917 |
1 |
|
|
T38 |
9 |
|
T21 |
198 |
|
T22 |
21 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4429841 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
auto[1] |
2017792 |
1 |
|
|
T38 |
135 |
|
T20 |
24 |
|
T21 |
1060 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
889627 |
1 |
|
|
T38 |
44 |
|
T20 |
17 |
|
T21 |
416 |
auto[1] |
auto[0] |
auto[1] |
128959 |
1 |
|
|
T38 |
3 |
|
T21 |
95 |
|
T22 |
14 |
auto[1] |
auto[1] |
auto[0] |
874248 |
1 |
|
|
T38 |
82 |
|
T20 |
7 |
|
T21 |
446 |
auto[1] |
auto[1] |
auto[1] |
124958 |
1 |
|
|
T38 |
6 |
|
T21 |
103 |
|
T22 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4434370 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
auto[1] |
2013263 |
1 |
|
|
T38 |
73 |
|
T20 |
34 |
|
T21 |
1124 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6196944 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
auto[1] |
250689 |
1 |
|
|
T38 |
11 |
|
T21 |
173 |
|
T22 |
23 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4453909 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
auto[1] |
1993724 |
1 |
|
|
T38 |
134 |
|
T20 |
22 |
|
T21 |
871 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
872604 |
1 |
|
|
T38 |
71 |
|
T20 |
5 |
|
T21 |
309 |
auto[1] |
auto[0] |
auto[1] |
125055 |
1 |
|
|
T38 |
7 |
|
T21 |
78 |
|
T22 |
11 |
auto[1] |
auto[1] |
auto[0] |
870431 |
1 |
|
|
T38 |
52 |
|
T20 |
17 |
|
T21 |
389 |
auto[1] |
auto[1] |
auto[1] |
125634 |
1 |
|
|
T38 |
4 |
|
T21 |
95 |
|
T22 |
12 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4440037 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
auto[1] |
2007596 |
1 |
|
|
T38 |
65 |
|
T20 |
41 |
|
T21 |
900 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6194151 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
auto[1] |
253482 |
1 |
|
|
T38 |
8 |
|
T20 |
1 |
|
T21 |
187 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4432266 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
auto[1] |
2015367 |
1 |
|
|
T38 |
122 |
|
T20 |
15 |
|
T21 |
1003 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
880349 |
1 |
|
|
T38 |
74 |
|
T20 |
6 |
|
T21 |
368 |
auto[1] |
auto[0] |
auto[1] |
126339 |
1 |
|
|
T38 |
6 |
|
T20 |
1 |
|
T21 |
85 |
auto[1] |
auto[1] |
auto[0] |
881536 |
1 |
|
|
T38 |
40 |
|
T20 |
8 |
|
T21 |
448 |
auto[1] |
auto[1] |
auto[1] |
127143 |
1 |
|
|
T38 |
2 |
|
T21 |
102 |
|
T22 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4437253 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
auto[1] |
2010380 |
1 |
|
|
T38 |
100 |
|
T20 |
39 |
|
T21 |
770 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6193765 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
auto[1] |
253868 |
1 |
|
|
T38 |
4 |
|
T21 |
175 |
|
T22 |
17 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4439284 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
auto[1] |
2008349 |
1 |
|
|
T38 |
74 |
|
T20 |
27 |
|
T21 |
970 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
874176 |
1 |
|
|
T38 |
37 |
|
T20 |
18 |
|
T21 |
512 |
auto[1] |
auto[0] |
auto[1] |
126679 |
1 |
|
|
T21 |
116 |
|
T22 |
12 |
|
T55 |
2 |
auto[1] |
auto[1] |
auto[0] |
880305 |
1 |
|
|
T38 |
33 |
|
T20 |
9 |
|
T21 |
283 |
auto[1] |
auto[1] |
auto[1] |
127189 |
1 |
|
|
T38 |
4 |
|
T21 |
59 |
|
T22 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4426234 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
auto[1] |
2021399 |
1 |
|
|
T38 |
72 |
|
T20 |
9 |
|
T21 |
1016 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6195688 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
auto[1] |
251945 |
1 |
|
|
T38 |
5 |
|
T20 |
1 |
|
T21 |
165 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4442492 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
auto[1] |
2005141 |
1 |
|
|
T38 |
50 |
|
T20 |
27 |
|
T21 |
912 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
875404 |
1 |
|
|
T38 |
22 |
|
T20 |
22 |
|
T21 |
405 |
auto[1] |
auto[0] |
auto[1] |
125980 |
1 |
|
|
T38 |
3 |
|
T20 |
1 |
|
T21 |
84 |
auto[1] |
auto[1] |
auto[0] |
877792 |
1 |
|
|
T38 |
23 |
|
T20 |
4 |
|
T21 |
342 |
auto[1] |
auto[1] |
auto[1] |
125965 |
1 |
|
|
T38 |
2 |
|
T21 |
81 |
|
T22 |
14 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4458075 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
auto[1] |
1989558 |
1 |
|
|
T38 |
68 |
|
T20 |
29 |
|
T21 |
647 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6193729 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
auto[1] |
253904 |
1 |
|
|
T38 |
4 |
|
T20 |
1 |
|
T21 |
154 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4428727 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
auto[1] |
2018906 |
1 |
|
|
T38 |
73 |
|
T20 |
24 |
|
T21 |
863 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
894605 |
1 |
|
|
T38 |
41 |
|
T20 |
17 |
|
T21 |
478 |
auto[1] |
auto[0] |
auto[1] |
128936 |
1 |
|
|
T38 |
4 |
|
T20 |
1 |
|
T21 |
100 |
auto[1] |
auto[1] |
auto[0] |
870397 |
1 |
|
|
T38 |
28 |
|
T20 |
6 |
|
T21 |
231 |
auto[1] |
auto[1] |
auto[1] |
124968 |
1 |
|
|
T21 |
54 |
|
T22 |
6 |
|
T55 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4430449 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
auto[1] |
2017184 |
1 |
|
|
T38 |
72 |
|
T20 |
36 |
|
T21 |
723 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6196437 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
auto[1] |
251196 |
1 |
|
|
T38 |
7 |
|
T21 |
149 |
|
T22 |
13 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4444245 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
auto[1] |
2003388 |
1 |
|
|
T38 |
107 |
|
T20 |
22 |
|
T21 |
801 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
875060 |
1 |
|
|
T38 |
58 |
|
T20 |
9 |
|
T21 |
391 |
auto[1] |
auto[0] |
auto[1] |
125225 |
1 |
|
|
T38 |
6 |
|
T21 |
88 |
|
T22 |
9 |
auto[1] |
auto[1] |
auto[0] |
877132 |
1 |
|
|
T38 |
42 |
|
T20 |
13 |
|
T21 |
261 |
auto[1] |
auto[1] |
auto[1] |
125971 |
1 |
|
|
T38 |
1 |
|
T21 |
61 |
|
T22 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4438295 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
auto[1] |
2009338 |
1 |
|
|
T38 |
82 |
|
T20 |
15 |
|
T21 |
1193 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6195852 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
auto[1] |
251781 |
1 |
|
|
T38 |
8 |
|
T20 |
1 |
|
T21 |
181 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4449673 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
auto[1] |
1997960 |
1 |
|
|
T38 |
69 |
|
T20 |
27 |
|
T21 |
1000 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
878461 |
1 |
|
|
T38 |
26 |
|
T20 |
18 |
|
T21 |
371 |
auto[1] |
auto[0] |
auto[1] |
126619 |
1 |
|
|
T38 |
3 |
|
T20 |
1 |
|
T21 |
86 |
auto[1] |
auto[1] |
auto[0] |
867718 |
1 |
|
|
T38 |
35 |
|
T20 |
8 |
|
T21 |
448 |
auto[1] |
auto[1] |
auto[1] |
125162 |
1 |
|
|
T38 |
5 |
|
T21 |
95 |
|
T22 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4446887 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
auto[1] |
2000746 |
1 |
|
|
T38 |
126 |
|
T20 |
42 |
|
T21 |
931 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6197270 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
auto[1] |
250363 |
1 |
|
|
T38 |
5 |
|
T21 |
163 |
|
T22 |
17 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4452537 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
auto[1] |
1995096 |
1 |
|
|
T38 |
64 |
|
T20 |
34 |
|
T21 |
867 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
883332 |
1 |
|
|
T38 |
13 |
|
T20 |
10 |
|
T21 |
331 |
auto[1] |
auto[0] |
auto[1] |
127644 |
1 |
|
|
T21 |
79 |
|
T22 |
6 |
|
T55 |
4 |
auto[1] |
auto[1] |
auto[0] |
861401 |
1 |
|
|
T38 |
46 |
|
T20 |
24 |
|
T21 |
373 |
auto[1] |
auto[1] |
auto[1] |
122719 |
1 |
|
|
T38 |
5 |
|
T21 |
84 |
|
T22 |
11 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4436810 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
auto[1] |
2010823 |
1 |
|
|
T38 |
104 |
|
T20 |
31 |
|
T21 |
735 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6195123 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
auto[1] |
252510 |
1 |
|
|
T38 |
6 |
|
T21 |
199 |
|
T22 |
21 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4443812 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
auto[1] |
2003821 |
1 |
|
|
T38 |
80 |
|
T20 |
26 |
|
T21 |
1068 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
881423 |
1 |
|
|
T38 |
28 |
|
T20 |
11 |
|
T21 |
562 |
auto[1] |
auto[0] |
auto[1] |
127048 |
1 |
|
|
T38 |
1 |
|
T21 |
128 |
|
T22 |
7 |
auto[1] |
auto[1] |
auto[0] |
869888 |
1 |
|
|
T38 |
46 |
|
T20 |
15 |
|
T21 |
307 |
auto[1] |
auto[1] |
auto[1] |
125462 |
1 |
|
|
T38 |
5 |
|
T21 |
71 |
|
T22 |
14 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4419865 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
auto[1] |
2027768 |
1 |
|
|
T38 |
95 |
|
T20 |
39 |
|
T21 |
1102 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6194932 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
auto[1] |
252701 |
1 |
|
|
T38 |
6 |
|
T21 |
190 |
|
T22 |
17 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4439797 |
1 |
|
|
T33 |
503 |
|
T34 |
364 |
|
T35 |
394 |
auto[1] |
2007836 |
1 |
|
|
T38 |
117 |
|
T20 |
14 |
|
T21 |
1069 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
873501 |
1 |
|
|
T38 |
39 |
|
T20 |
4 |
|
T21 |
403 |
auto[1] |
auto[0] |
auto[1] |
125309 |
1 |
|
|
T38 |
1 |
|
T21 |
85 |
|
T22 |
6 |
auto[1] |
auto[1] |
auto[0] |
881634 |
1 |
|
|
T38 |
72 |
|
T20 |
10 |
|
T21 |
476 |
auto[1] |
auto[1] |
auto[1] |
127392 |
1 |
|
|
T38 |
5 |
|
T21 |
105 |
|
T22 |
11 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |