Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1273848	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4479872

1

T23

157

T24

394

T25

400

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2580775	1			T23	199		T24	125		T25	96
values[0x0]	1581792	1			T23	25		T24	151		T25	162
values[0x1]	1591153	1			T23	33		T24	173		T25	198

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1014187	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4739533

1

T23

175

T24

408

T25

410

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	19445	1			T29	5		T32	3		T55	1
valid_sources[0x01]	23402	1			T24	12		T26	1		T28	1
valid_sources[0x02]	18945	1			T26	4		T28	1		T29	1
valid_sources[0x03]	18858	1			T28	1		T29	7		T32	1
valid_sources[0x04]	21941	1			T24	1		T28	3		T29	2
valid_sources[0x05]	19027	1			T28	1		T29	3		T32	8
valid_sources[0x06]	19178	1			T24	14		T28	1		T29	4
valid_sources[0x07]	23909	1			T26	1		T29	8		T32	7
valid_sources[0x08]	19745	1			T28	1		T29	5		T32	3
valid_sources[0x09]	22210	1			T28	1		T29	4		T32	6
valid_sources[0x0a]	20036	1			T29	5		T32	9		T43	3
valid_sources[0x0b]	21387	1			T28	2		T29	3		T32	3
valid_sources[0x0c]	18962	1			T26	10		T28	2		T29	6
valid_sources[0x0d]	92249	1			T29	3		T32	7		T57	2
valid_sources[0x0e]	109926	1			T28	3		T29	9		T32	3
valid_sources[0x0f]	19008	1			T24	4		T28	2		T29	4
valid_sources[0x10]	19211	1			T28	1		T29	6		T32	5
valid_sources[0x11]	18948	1			T26	2		T28	1		T29	3
valid_sources[0x12]	19842	1			T28	1		T29	3		T32	6
valid_sources[0x13]	18780	1			T26	4		T28	3		T29	3
valid_sources[0x14]	25470	1			T24	2		T28	4		T29	5
valid_sources[0x15]	21077	1			T28	1		T29	5		T32	2
valid_sources[0x16]	70928	1			T24	1		T28	4		T29	1
valid_sources[0x17]	19786	1			T24	2		T26	3		T29	5
valid_sources[0x18]	25568	1			T26	1		T28	3		T32	12
valid_sources[0x19]	19573	1			T24	7		T26	5		T28	1
valid_sources[0x1a]	20188	1			T28	1		T29	5		T32	4
valid_sources[0x1b]	20919	1			T28	3		T29	1		T32	6
valid_sources[0x1c]	23323	1			T24	1		T26	6		T28	2
valid_sources[0x1d]	19278	1			T26	1		T28	1		T29	4
valid_sources[0x1e]	19666	1			T28	1		T29	1		T32	6
valid_sources[0x1f]	19006	1			T28	1		T29	2		T32	6
valid_sources[0x20]	20369	1			T28	3		T29	6		T32	9
valid_sources[0x21]	19148	1			T28	1		T29	6		T32	3
valid_sources[0x22]	20053	1			T25	456		T28	3		T29	5
valid_sources[0x23]	19454	1			T26	3		T28	3		T29	9
valid_sources[0x24]	19536	1			T28	2		T29	5		T32	4
valid_sources[0x25]	24071	1			T28	2		T29	3		T32	7
valid_sources[0x26]	21925	1			T24	1		T28	3		T29	5
valid_sources[0x27]	20032	1			T26	1		T28	3		T29	1
valid_sources[0x28]	18676	1			T28	2		T29	4		T32	7
valid_sources[0x29]	19990	1			T28	2		T29	7		T32	9
valid_sources[0x2a]	19507	1			T24	18		T28	3		T29	4
valid_sources[0x2b]	19792	1			T28	4		T29	3		T32	6
valid_sources[0x2c]	22079	1			T29	2		T31	271		T32	4
valid_sources[0x2d]	19026	1			T24	2		T28	2		T29	4
valid_sources[0x2e]	22601	1			T24	3		T26	1		T29	7
valid_sources[0x2f]	20876	1			T26	1		T28	1		T29	4
valid_sources[0x30]	19226	1			T29	8		T32	1		T57	8
valid_sources[0x31]	19091	1			T28	4		T29	7		T32	2
valid_sources[0x32]	19445	1			T28	3		T29	2		T32	2
valid_sources[0x33]	19985	1			T28	1		T29	6		T32	6
valid_sources[0x34]	22373	1			T28	2		T29	9		T32	16
valid_sources[0x35]	19182	1			T28	2		T29	4		T32	9
valid_sources[0x36]	25234	1			T29	7		T32	6		T55	9
valid_sources[0x37]	18371	1			T24	9		T29	2		T32	6
valid_sources[0x38]	19048	1			T24	6		T29	4		T32	6
valid_sources[0x39]	21446	1			T28	2		T29	3		T32	13
valid_sources[0x3a]	18947	1			T29	3		T32	1		T43	2
valid_sources[0x3b]	21957	1			T24	1		T29	5		T32	4
valid_sources[0x3c]	19890	1			T28	2		T29	3		T32	6
valid_sources[0x3d]	39655	1			T24	10		T26	2		T28	2
valid_sources[0x3e]	39443	1			T28	3		T29	5		T32	3
valid_sources[0x3f]	19960	1			T28	3		T29	4		T32	3
valid_sources[0x40]	18762	1			T28	3		T29	4		T32	3
valid_sources[0x41]	21938	1			T28	1		T29	10		T32	7
valid_sources[0x42]	19696	1			T26	5		T28	7		T29	4
valid_sources[0x43]	20424	1			T24	1		T29	5		T32	2
valid_sources[0x44]	22279	1			T26	1		T28	1		T29	4
valid_sources[0x45]	20392	1			T26	5		T28	2		T29	6
valid_sources[0x46]	19236	1			T24	6		T28	2		T29	6
valid_sources[0x47]	19836	1			T24	2		T28	1		T29	4
valid_sources[0x48]	21576	1			T29	4		T32	9		T57	1
valid_sources[0x49]	18976	1			T24	4		T28	3		T29	1
valid_sources[0x4a]	19354	1			T26	5		T28	2		T29	4
valid_sources[0x4b]	23023	1			T28	2		T29	3		T32	14
valid_sources[0x4c]	20809	1			T26	2		T28	1		T29	9
valid_sources[0x4d]	20115	1			T28	2		T29	6		T32	12
valid_sources[0x4e]	20335	1			T28	4		T29	3		T32	6
valid_sources[0x4f]	18939	1			T26	1		T28	3		T29	3
valid_sources[0x50]	21560	1			T29	2		T32	8		T55	1
valid_sources[0x51]	22200	1			T26	1		T28	1		T29	9
valid_sources[0x52]	19943	1			T28	2		T29	6		T32	1
valid_sources[0x53]	22809	1			T28	3		T29	2		T32	10
valid_sources[0x54]	18599	1			T28	3		T29	3		T32	2
valid_sources[0x55]	20761	1			T24	2		T29	2		T32	9
valid_sources[0x56]	19903	1			T26	2		T28	5		T29	5
valid_sources[0x57]	18328	1			T24	7		T28	2		T29	4
valid_sources[0x58]	20775	1			T28	2		T29	7		T40	11
valid_sources[0x59]	19943	1			T24	1		T28	2		T29	8
valid_sources[0x5a]	21890	1			T24	1		T28	2		T29	6
valid_sources[0x5b]	20239	1			T26	1		T28	3		T29	4
valid_sources[0x5c]	18610	1			T28	2		T29	3		T32	5
valid_sources[0x5d]	21026	1			T24	5		T26	2		T28	3
valid_sources[0x5e]	20596	1			T28	1		T29	4		T32	8
valid_sources[0x5f]	20076	1			T28	1		T29	2		T32	4
valid_sources[0x60]	22624	1			T29	1		T32	5		T55	2
valid_sources[0x61]	23464	1			T24	9		T29	5		T32	11
valid_sources[0x62]	65289	1			T28	1		T29	4		T32	10
valid_sources[0x63]	19984	1			T24	5		T26	3		T27	371
valid_sources[0x64]	19181	1			T24	5		T28	2		T29	4
valid_sources[0x65]	62217	1			T28	1		T29	5		T32	6
valid_sources[0x66]	27652	1			T29	6		T32	8		T57	4
valid_sources[0x67]	19831	1			T24	13		T28	2		T29	2
valid_sources[0x68]	20027	1			T24	2		T29	8		T32	13
valid_sources[0x69]	18895	1			T28	4		T29	1		T32	4
valid_sources[0x6a]	21322	1			T28	1		T29	5		T32	4
valid_sources[0x6b]	20076	1			T28	1		T29	1		T55	1
valid_sources[0x6c]	19593	1			T28	2		T29	11		T32	7
valid_sources[0x6d]	19631	1			T29	8		T32	9		T57	3
valid_sources[0x6e]	22010	1			T28	1		T29	2		T32	6
valid_sources[0x6f]	20539	1			T28	7		T29	1		T32	3
valid_sources[0x70]	21282	1			T28	2		T29	3		T32	4
valid_sources[0x71]	23520	1			T26	1		T28	5		T29	2
valid_sources[0x72]	20140	1			T28	4		T29	4		T32	8
valid_sources[0x73]	18824	1			T29	1		T32	7		T55	1
valid_sources[0x74]	22550	1			T26	3		T28	6		T29	3
valid_sources[0x75]	19018	1			T26	2		T29	7		T32	11
valid_sources[0x76]	22135	1			T28	1		T29	8		T32	8
valid_sources[0x77]	19361	1			T28	1		T29	9		T32	9
valid_sources[0x78]	23765	1			T28	4		T29	2		T32	4
valid_sources[0x79]	20282	1			T32	6		T55	2		T40	27
valid_sources[0x7a]	22181	1			T24	6		T26	5		T28	1
valid_sources[0x7b]	24000	1			T28	3		T29	2		T32	12
valid_sources[0x7c]	19580	1			T28	3		T29	3		T32	4
valid_sources[0x7d]	21634	1			T28	1		T29	5		T32	4
valid_sources[0x7e]	19343	1			T24	20		T29	2		T32	1
valid_sources[0x7f]	19176	1			T24	9		T29	4		T32	7
valid_sources[0x80]	22571	1			T24	4		T28	2		T29	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1319479

1

T23

99

T24

70

T25

40

values[0x0]

all_enables

biggest_size

1580196

1

T23

25

T24

151

T25

162

values[0x1]

all_enables

biggest_size

1580197

1

T23

33

T24

173

T25

198